/* SPDX-License-Identifier: GPL-2.0
 * aw882xx_pid_1852_reg.h
 *
 * Copyright (c) 2020 AWINIC Technology CO., LTD
 *
 * Author: Nick Li <liweilei@awinic.com.cn>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */

#ifndef __AW882XX_PID_1852_REG_H__
#define __AW882XX_PID_1852_REG_H__

#define AW_PID_1852_MONITOR_FILE	"aw882xx_pid_1852_monitor.bin"

/* registers list */
#define AW_PID_1852_ID_REG				(0x00)
#define AW_PID_1852_SYSST_REG			(0x01)
#define AW_PID_1852_SYSINT_REG			(0x02)
#define AW_PID_1852_SYSINTM_REG			(0x03)
#define AW_PID_1852_SYSCTRL_REG			(0x04)
#define AW_PID_1852_SYSCTRL2_REG		(0x05)
#define AW_PID_1852_I2SCTRL_REG			(0x06)
#define AW_PID_1852_I2SCFG1_REG			(0x07)
#define AW_PID_1852_I2SCFG2_REG			(0x08)
#define AW_PID_1852_HAGCCFG1_REG		(0x09)
#define AW_PID_1852_HAGCCFG2_REG		(0x0A)
#define AW_PID_1852_HAGCCFG3_REG		(0x0B)
#define AW_PID_1852_HAGCCFG4_REG		(0x0C)
#define AW_PID_1852_HAGCCFG5_REG		(0x0D)
#define AW_PID_1852_HAGCCFG6_REG		(0x0E)
#define AW_PID_1852_HAGCCFG7_REG		(0x0F)
#define AW_PID_1852_HAGCST_REG			(0x10)
#define AW_PID_1852_PRODID_REG			(0x11)
#define AW_PID_1852_VBAT_REG			(0x12)
#define AW_PID_1852_TEMP_REG			(0x13)
#define AW_PID_1852_PVDD_REG			(0x14)
#define AW_PID_1852_DBGCTRL_REG			(0x20)
#define AW_PID_1852_I2SINT_REG			(0x21)
#define AW_PID_1852_I2SCAPCNT_REG		(0x22)
#define AW_PID_1852_CRCIN_REG			(0x38)
#define AW_PID_1852_CRCOUT_REG			(0x39)
#define AW_PID_1852_VSNCTRL1_REG		(0x50)
#define AW_PID_1852_ISNCTRL1_REG		(0x52)
#define AW_PID_1852_ISNCTRL2_REG		(0x53)
#define AW_PID_1852_VTMCTRL1_REG		(0x54)
#define AW_PID_1852_VTMCTRL2_REG		(0x55)
#define AW_PID_1852_VTMCTRL3_REG		(0x56)
#define AW_PID_1852_ISNDAT_REG			(0x57)
#define AW_PID_1852_VSNDAT_REG			(0x58)
#define AW_PID_1852_PWMCTRL_REG			(0x59)
#define AW_PID_1852_PWMCTRL2_REG		(0x5A)
#define AW_PID_1852_BSTCTRL1_REG		(0x60)
#define AW_PID_1852_BSTCTRL2_REG		(0x61)
#define AW_PID_1852_BSTCTRL3_REG		(0x62)
#define AW_PID_1852_BSTDBG1_REG			(0x63)
#define AW_PID_1852_BSTDBG2_REG			(0x64)
#define AW_PID_1852_BSTDBG3_REG			(0x65)
#define AW_PID_1852_PLLCTRL1_REG		(0x66)
#define AW_PID_1852_PLLCTRL2_REG		(0x67)
#define AW_PID_1852_PLLCTRL3_REG		(0x68)
#define AW_PID_1852_CDACTRL1_REG		(0x69)
#define AW_PID_1852_CDACTRL2_REG		(0x6A)
#define AW_PID_1852_SADCCTRL_REG		(0x6B)
#define AW_PID_1852_TESTCTRL1_REG		(0x70)
#define AW_PID_1852_TESTCTRL2_REG		(0x71)
#define AW_PID_1852_EFCTRL1_REG			(0x72)
#define AW_PID_1852_EFCTRL2_REG			(0x73)
#define AW_PID_1852_EFWH_REG			(0x74)
#define AW_PID_1852_EFWM2_REG			(0x75)
#define AW_PID_1852_EFWM1_REG			(0x76)
#define AW_PID_1852_EFWL_REG			(0x77)
#define AW_PID_1852_EFRH_REG			(0x78)
#define AW_PID_1852_EFRM2_REG			(0x79)
#define AW_PID_1852_EFRM1_REG			(0x7A)
#define AW_PID_1852_EFRL_REG			(0x7B)
#define AW_PID_1852_TESTDET_REG			(0x7C)

/********************************************
 * Register Access
 *******************************************/
#define AW_PID_1852_REG_MAX				(0x7D)


#define AW_PID_1852_REG_NONE_ACCESS					(0)
#define AW_PID_1852_REG_RD_ACCESS					(1 << 0)
#define AW_PID_1852_REG_WR_ACCESS					(1 << 1)


static const unsigned char aw_pid_1852_reg_access[AW_PID_1852_REG_MAX] = {
	[AW_PID_1852_ID_REG]		= (AW_PID_1852_REG_RD_ACCESS),
	[AW_PID_1852_SYSST_REG]		= (AW_PID_1852_REG_RD_ACCESS),
	[AW_PID_1852_SYSINT_REG]	= (AW_PID_1852_REG_RD_ACCESS),
	[AW_PID_1852_SYSINTM_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_SYSCTRL_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_SYSCTRL2_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_I2SCTRL_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_I2SCFG1_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_I2SCFG2_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_HAGCCFG1_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_HAGCCFG2_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_HAGCCFG3_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_HAGCCFG4_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_HAGCCFG5_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_HAGCCFG6_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_HAGCCFG7_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_HAGCST_REG]	= (AW_PID_1852_REG_RD_ACCESS),
	[AW_PID_1852_PRODID_REG]	= (AW_PID_1852_REG_RD_ACCESS),
	[AW_PID_1852_VBAT_REG]		= (AW_PID_1852_REG_RD_ACCESS),
	[AW_PID_1852_TEMP_REG]		= (AW_PID_1852_REG_RD_ACCESS),
	[AW_PID_1852_PVDD_REG]		= (AW_PID_1852_REG_RD_ACCESS),
	[AW_PID_1852_DBGCTRL_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_I2SINT_REG]	= (AW_PID_1852_REG_RD_ACCESS),
	[AW_PID_1852_I2SCAPCNT_REG]	= (AW_PID_1852_REG_RD_ACCESS),
	[AW_PID_1852_CRCIN_REG]		= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_CRCOUT_REG]	= (AW_PID_1852_REG_RD_ACCESS),
	[AW_PID_1852_VSNCTRL1_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_ISNCTRL1_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_ISNCTRL2_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_VTMCTRL1_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_VTMCTRL2_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_VTMCTRL3_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_ISNDAT_REG]	= (AW_PID_1852_REG_RD_ACCESS),
	[AW_PID_1852_VSNDAT_REG]	= (AW_PID_1852_REG_RD_ACCESS),
	[AW_PID_1852_PWMCTRL_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_PWMCTRL2_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_BSTCTRL1_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_BSTCTRL2_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_BSTCTRL3_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_BSTDBG1_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_BSTDBG2_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_BSTDBG3_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_PLLCTRL1_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_PLLCTRL2_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_PLLCTRL3_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_CDACTRL1_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_CDACTRL2_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_SADCCTRL_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_TESTCTRL1_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_TESTCTRL2_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_EFCTRL1_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_EFCTRL2_REG]	= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_EFWH_REG]		= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_EFWM2_REG]		= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_EFWM1_REG]		= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_EFWL_REG]		= (AW_PID_1852_REG_RD_ACCESS | AW_PID_1852_REG_WR_ACCESS),
	[AW_PID_1852_EFRH_REG]		= (AW_PID_1852_REG_RD_ACCESS),
	[AW_PID_1852_EFRM2_REG]		= (AW_PID_1852_REG_RD_ACCESS),
	[AW_PID_1852_EFRM1_REG]		= (AW_PID_1852_REG_RD_ACCESS),
	[AW_PID_1852_EFRL_REG]		= (AW_PID_1852_REG_RD_ACCESS),
	[AW_PID_1852_TESTDET_REG]	= (AW_PID_1852_REG_RD_ACCESS),
};

/* detail information of registers begin */
/* ID (0x00) detail */
/* IDCODE bit 15:0 (ID 0x00) */
#define AW_PID_1852_IDCODE_START_BIT	(0)
#define AW_PID_1852_IDCODE_BITS_LEN		(16)
#define AW_PID_1852_IDCODE_MASK			\
	(~(((1<<AW_PID_1852_IDCODE_BITS_LEN)-1) << AW_PID_1852_IDCODE_START_BIT))

#define AW_PID_1852_IDCODE_DEFAULT_VALUE	(0x1852)
#define AW_PID_1852_IDCODE_DEFAULT		\
	(AW_PID_1852_IDCODE_DEFAULT_VALUE << AW_PID_1852_IDCODE_START_BIT)

/* default value of ID (0x00) */
/* #define AW_PID_1852_ID_DEFAULT		(0x1852) */

/* SYSST (0x01) detail */
/* OVP2S bit 15 (SYSST 0x01) */
#define AW_PID_1852_OVP2S_START_BIT		(15)
#define AW_PID_1852_OVP2S_BITS_LEN		(1)
#define AW_PID_1852_OVP2S_MASK			\
	(~(((1<<AW_PID_1852_OVP2S_BITS_LEN)-1) << AW_PID_1852_OVP2S_START_BIT))

#define AW_PID_1852_OVP2S_DEFAULT_VALUE	(0)
#define AW_PID_1852_OVP2S_DEFAULT		\
	(AW_PID_1852_OVP2S_DEFAULT_VALUE << AW_PID_1852_OVP2S_START_BIT)

/* UVLS bit 14 (SYSST 0x01) */
#define AW_PID_1852_UVLS_START_BIT		(14)
#define AW_PID_1852_UVLS_BITS_LEN		(1)
#define AW_PID_1852_UVLS_MASK			\
	(~(((1<<AW_PID_1852_UVLS_BITS_LEN)-1) << AW_PID_1852_UVLS_START_BIT))

#define AW_PID_1852_UVLS_VDD_ABOVE_2P8V	(0)
#define AW_PID_1852_UVLS_VDD_ABOVE_2P8V_VALUE	\
	(AW_PID_1852_UVLS_VDD_ABOVE_2P8V << AW_PID_1852_UVLS_START_BIT)

#define AW_PID_1852_UVLS_VDD_BELOW_2P8V	(1)
#define AW_PID_1852_UVLS_VDD_BELOW_2P8V_VALUE	\
	(AW_PID_1852_UVLS_VDD_BELOW_2P8V << AW_PID_1852_UVLS_START_BIT)

#define AW_PID_1852_UVLS_DEFAULT_VALUE	(0)
#define AW_PID_1852_UVLS_DEFAULT		\
	(AW_PID_1852_UVLS_DEFAULT_VALUE << AW_PID_1852_UVLS_START_BIT)

/* ADPS bit 13 (SYSST 0x01) */
#define AW_PID_1852_ADPS_START_BIT		(13)
#define AW_PID_1852_ADPS_BITS_LEN		(1)
#define AW_PID_1852_ADPS_MASK			\
	(~(((1<<AW_PID_1852_ADPS_BITS_LEN)-1) << AW_PID_1852_ADPS_START_BIT))

#define AW_PID_1852_ADPS_TRANSPARENT	(0)
#define AW_PID_1852_ADPS_TRANSPARENT_VALUE	\
	(AW_PID_1852_ADPS_TRANSPARENT << AW_PID_1852_ADPS_START_BIT)

#define AW_PID_1852_ADPS_BOOST			(1)
#define AW_PID_1852_ADPS_BOOST_VALUE	\
	(AW_PID_1852_ADPS_BOOST << AW_PID_1852_ADPS_START_BIT)

#define AW_PID_1852_ADPS_DEFAULT_VALUE	(0)
#define AW_PID_1852_ADPS_DEFAULT		\
	(AW_PID_1852_ADPS_DEFAULT_VALUE << AW_PID_1852_ADPS_START_BIT)

/* BSTOCS bit 11 (SYSST 0x01) */
#define AW_PID_1852_BSTOCS_START_BIT	(11)
#define AW_PID_1852_BSTOCS_BITS_LEN		(1)
#define AW_PID_1852_BSTOCS_MASK			\
	(~(((1<<AW_PID_1852_BSTOCS_BITS_LEN)-1) << AW_PID_1852_BSTOCS_START_BIT))

#define AW_PID_1852_BSTOCS_DEFAULT_VALUE	(0)
#define AW_PID_1852_BSTOCS_DEFAULT		\
	(AW_PID_1852_BSTOCS_DEFAULT_VALUE << AW_PID_1852_BSTOCS_START_BIT)

#define AW_PID_1852_BSTOCS_TRIG				(1)
#define AW_PID_1852_BSTOCS_TRIG_VALUE		\
	(AW_PID_1852_BSTOCS_TRIG << AW_PID_1852_BSTOCS_START_BIT)

/* OVPS bit 10 (SYSST 0x01) */
#define AW_PID_1852_OVPS_START_BIT		(10)
#define AW_PID_1852_OVPS_BITS_LEN		(1)
#define AW_PID_1852_OVPS_MASK			\
	(~(((1<<AW_PID_1852_OVPS_BITS_LEN)-1) << AW_PID_1852_OVPS_START_BIT))

#define AW_PID_1852_OVPS_DEFAULT_VALUE	(0)
#define AW_PID_1852_OVPS_DEFAULT		\
	(AW_PID_1852_OVPS_DEFAULT_VALUE << AW_PID_1852_OVPS_START_BIT)

/* BSTS bit 9 (SYSST 0x01) */
#define AW_PID_1852_BSTS_START_BIT		(9)
#define AW_PID_1852_BSTS_BITS_LEN		(1)
#define AW_PID_1852_BSTS_MASK			\
	(~(((1<<AW_PID_1852_BSTS_BITS_LEN)-1) << AW_PID_1852_BSTS_START_BIT))

#define AW_PID_1852_BSTS_NOT_FINISHED	(0)
#define AW_PID_1852_BSTS_NOT_FINISHED_VALUE	\
	(AW_PID_1852_BSTS_NOT_FINISHED << AW_PID_1852_BSTS_START_BIT)

#define AW_PID_1852_BSTS_FINISHED		(1)
#define AW_PID_1852_BSTS_FINISHED_VALUE	\
	(AW_PID_1852_BSTS_FINISHED << AW_PID_1852_BSTS_START_BIT)

#define AW_PID_1852_BSTS_DEFAULT_VALUE	(0)
#define AW_PID_1852_BSTS_DEFAULT		\
	(AW_PID_1852_BSTS_DEFAULT_VALUE << AW_PID_1852_BSTS_START_BIT)

/* SWS bit 8 (SYSST 0x01) */
#define AW_PID_1852_SWS_START_BIT		(8)
#define AW_PID_1852_SWS_BITS_LEN		(1)
#define AW_PID_1852_SWS_MASK			\
	(~(((1<<AW_PID_1852_SWS_BITS_LEN)-1) << AW_PID_1852_SWS_START_BIT))

#define AW_PID_1852_SWS_NOT_SWITCHING	(0)
#define AW_PID_1852_SWS_NOT_SWITCHING_VALUE	\
	(AW_PID_1852_SWS_NOT_SWITCHING << AW_PID_1852_SWS_START_BIT)

#define AW_PID_1852_SWS_SWITCHING		(1)
#define AW_PID_1852_SWS_SWITCHING_VALUE	\
	(AW_PID_1852_SWS_SWITCHING << AW_PID_1852_SWS_START_BIT)

#define AW_PID_1852_SWS_DEFAULT_VALUE	(0)
#define AW_PID_1852_SWS_DEFAULT			\
	(AW_PID_1852_SWS_DEFAULT_VALUE << AW_PID_1852_SWS_START_BIT)

/* CLIPS bit 7 (SYSST 0x01) */
#define AW_PID_1852_CLIPS_START_BIT		(7)
#define AW_PID_1852_CLIPS_BITS_LEN		(1)
#define AW_PID_1852_CLIPS_MASK			\
	(~(((1<<AW_PID_1852_CLIPS_BITS_LEN)-1) << AW_PID_1852_CLIPS_START_BIT))

#define AW_PID_1852_CLIPS_NOT_CLIPPING	(0)
#define AW_PID_1852_CLIPS_NOT_CLIPPING_VALUE	\
	(AW_PID_1852_CLIPS_NOT_CLIPPING << AW_PID_1852_CLIPS_START_BIT)

#define AW_PID_1852_CLIPS_CLIPPING		(1)
#define AW_PID_1852_CLIPS_CLIPPING_VALUE	\
	(AW_PID_1852_CLIPS_CLIPPING << AW_PID_1852_CLIPS_START_BIT)

#define AW_PID_1852_CLIPS_DEFAULT_VALUE	(0)
#define AW_PID_1852_CLIPS_DEFAULT		\
	(AW_PID_1852_CLIPS_DEFAULT_VALUE << AW_PID_1852_CLIPS_START_BIT)

/* NOCLKS bit 5 (SYSST 0x01) */
#define AW_PID_1852_NOCLKS_START_BIT	(5)
#define AW_PID_1852_NOCLKS_BITS_LEN		(1)
#define AW_PID_1852_NOCLKS_MASK			\
	(~(((1<<AW_PID_1852_NOCLKS_BITS_LEN)-1) << AW_PID_1852_NOCLKS_START_BIT))

#define AW_PID_1852_NOCLKS_NONE				(0)
#define AW_PID_1852_NOCLKS_NONE_VALUE		\
		(AW_PID_1852_NOCLKS_NONE << AW_PID_1852_NOCLKS_START_BIT)

#define AW_PID_1852_NOCLKS_TRIG				(1)
#define AW_PID_1852_NOCLKS_TRIG_VALUE		\
	(AW_PID_1852_NOCLKS_NONE << AW_PID_1852_NOCLKS_START_BIT)

#define AW_PID_1852_NOCLKS_DEFAULT_VALUE	(0)
#define AW_PID_1852_NOCLKS_DEFAULT		\
	(AW_PID_1852_NOCLKS_DEFAULT_VALUE << AW_PID_1852_NOCLKS_START_BIT)

/* CLKS bit 4 (SYSST 0x01) */
#define AW_PID_1852_CLKS_START_BIT		(4)
#define AW_PID_1852_CLKS_BITS_LEN		(1)
#define AW_PID_1852_CLKS_MASK			\
	(~(((1<<AW_PID_1852_CLKS_BITS_LEN)-1) << AW_PID_1852_CLKS_START_BIT))

#define AW_PID_1852_CLKS_DEFAULT_VALUE	(0)
#define AW_PID_1852_CLKS_DEFAULT		\
	(AW_PID_1852_CLKS_DEFAULT_VALUE << AW_PID_1852_CLKS_START_BIT)

#define AW_PID_1852_CLKS_TRIG				(1)
#define AW_PID_1852_CLKS_TRIG_VALUE			\
	(AW_PID_1852_CLKS_TRIG << AW_PID_1852_CLKS_START_BIT)

/* OCDS bit 3 (SYSST 0x01) */
#define AW_PID_1852_OCDS_START_BIT		(3)
#define AW_PID_1852_OCDS_BITS_LEN		(1)
#define AW_PID_1852_OCDS_MASK			\
	(~(((1<<AW_PID_1852_OCDS_BITS_LEN)-1) << AW_PID_1852_OCDS_START_BIT))

#define AW_PID_1852_OCDS_DEFAULT_VALUE	(0)
#define AW_PID_1852_OCDS_DEFAULT		\
	(AW_PID_1852_OCDS_DEFAULT_VALUE << AW_PID_1852_OCDS_START_BIT)

#define AW_PID_1852_OCDS_TRIG				(1)
#define AW_PID_1852_OCDS_TRIG_VALUE			\
	(AW_PID_1852_OCDS_TRIG << AW_PID_1852_OCDS_START_BIT)

/* CLIP_PRES bit 2 (SYSST 0x01) */
#define AW_PID_1852_CLIP_PRES_START_BIT	(2)
#define AW_PID_1852_CLIP_PRES_BITS_LEN	(1)
#define AW_PID_1852_CLIP_PRES_MASK		\
	(~(((1<<AW_PID_1852_CLIP_PRES_BITS_LEN)-1) << AW_PID_1852_CLIP_PRES_START_BIT))

#define AW_PID_1852_CLIP_PRES_DEFAULT_VALUE	(0)
#define AW_PID_1852_CLIP_PRES_DEFAULT	\
	(AW_PID_1852_CLIP_PRES_DEFAULT_VALUE << AW_PID_1852_CLIP_PRES_START_BIT)

/* OTHS bit 1 (SYSST 0x01) */
#define AW_PID_1852_OTHS_START_BIT		(1)
#define AW_PID_1852_OTHS_BITS_LEN		(1)
#define AW_PID_1852_OTHS_MASK			\
	(~(((1<<AW_PID_1852_OTHS_BITS_LEN)-1) << AW_PID_1852_OTHS_START_BIT))

#define AW_PID_1852_OTHS_DEFAULT_VALUE	(0)
#define AW_PID_1852_OTHS_DEFAULT		\
	(AW_PID_1852_OTHS_DEFAULT_VALUE << AW_PID_1852_OTHS_START_BIT)

#define AW_PID_1852_OTHS_TRIG				(1)
#define AW_PID_1852_OTHS_TRIG_VALUE			\
		(AW_PID_1852_OTHS_TRIG << AW_PID_1852_OTHS_START_BIT)

/* PLLS bit 0 (SYSST 0x01) */
#define AW_PID_1852_PLLS_START_BIT		(0)
#define AW_PID_1852_PLLS_BITS_LEN		(1)
#define AW_PID_1852_PLLS_MASK			\
	(~(((1<<AW_PID_1852_PLLS_BITS_LEN)-1) << AW_PID_1852_PLLS_START_BIT))

#define AW_PID_1852_PLLS_UNLOCKED		(0)
#define AW_PID_1852_PLLS_UNLOCKED_VALUE	\
	(AW_PID_1852_PLLS_UNLOCKED << AW_PID_1852_PLLS_START_BIT)

#define AW_PID_1852_PLLS_LOCKED			(1)
#define AW_PID_1852_PLLS_LOCKED_VALUE	\
	(AW_PID_1852_PLLS_LOCKED << AW_PID_1852_PLLS_START_BIT)

#define AW_PID_1852_PLLS_DEFAULT_VALUE	(0)
#define AW_PID_1852_PLLS_DEFAULT		\
	(AW_PID_1852_PLLS_DEFAULT_VALUE << AW_PID_1852_PLLS_START_BIT)

#define AW_PID_1852_SYSST_CHECK_MASK \
	(~(AW_PID_1852_UVLS_VDD_BELOW_2P8V_VALUE | \
	AW_PID_1852_BSTOCS_TRIG_VALUE | \
	AW_PID_1852_BSTS_FINISHED_VALUE | \
	AW_PID_1852_SWS_SWITCHING_VALUE | \
	AW_PID_1852_NOCLKS_TRIG_VALUE | \
	AW_PID_1852_CLKS_TRIG_VALUE | \
	AW_PID_1852_OCDS_TRIG_VALUE | \
	AW_PID_1852_OTHS_TRIG_VALUE | \
	AW_PID_1852_PLLS_LOCKED_VALUE))

#define AW_PID_1852_SYSST_CHECK \
	(AW_PID_1852_BSTS_FINISHED_VALUE | \
	AW_PID_1852_SWS_SWITCHING_VALUE | \
	AW_PID_1852_CLKS_TRIG_VALUE | \
	AW_PID_1852_PLLS_LOCKED_VALUE)

#define AW_PID_1852_IIS_CHECK_MASK \
	(~(AW_PID_1852_UVLS_VDD_BELOW_2P8V_VALUE | \
	AW_PID_1852_NOCLKS_TRIG_VALUE | \
	AW_PID_1852_CLKS_TRIG_VALUE | \
	AW_PID_1852_OCDS_TRIG_VALUE | \
	AW_PID_1852_OTHS_TRIG_VALUE | \
	AW_PID_1852_PLLS_LOCKED_VALUE))

#define AW_PID_1852_IIS_CHECK \
	(AW_PID_1852_CLKS_TRIG_VALUE | \
	AW_PID_1852_PLLS_LOCKED_VALUE)

/* default value of SYSST (0x01) */
/* #define AW_PID_1852_SYSST_DEFAULT		(0x0000) */

/* SYSINT (0x02) detail */
/* OVP2I bit 15 (SYSINT 0x02) */
#define AW_PID_1852_OVP2I_START_BIT		(15)
#define AW_PID_1852_OVP2I_BITS_LEN		(1)
#define AW_PID_1852_OVP2I_MASK			\
	(~(((1<<AW_PID_1852_OVP2I_BITS_LEN)-1) << AW_PID_1852_OVP2I_START_BIT))

#define AW_PID_1852_OVP2I_DEFAULT_VALUE	(0)
#define AW_PID_1852_OVP2I_DEFAULT		\
	(AW_PID_1852_OVP2I_DEFAULT_VALUE << AW_PID_1852_OVP2I_START_BIT)

/* UVLI bit 14 (SYSINT 0x02) */
#define AW_PID_1852_UVLI_START_BIT		(14)
#define AW_PID_1852_UVLI_BITS_LEN		(1)
#define AW_PID_1852_UVLI_MASK			\
	(~(((1<<AW_PID_1852_UVLI_BITS_LEN)-1) << AW_PID_1852_UVLI_START_BIT))

#define AW_PID_1852_UVLI_DEFAULT_VALUE	(0)
#define AW_PID_1852_UVLI_DEFAULT		\
	(AW_PID_1852_UVLI_DEFAULT_VALUE << AW_PID_1852_UVLI_START_BIT)

/* ADPI bit 13 (SYSINT 0x02) */
#define AW_PID_1852_ADPI_START_BIT		(13)
#define AW_PID_1852_ADPI_BITS_LEN		(1)
#define AW_PID_1852_ADPI_MASK			\
	(~(((1<<AW_PID_1852_ADPI_BITS_LEN)-1) << AW_PID_1852_ADPI_START_BIT))

#define AW_PID_1852_ADPI_DEFAULT_VALUE	(0)
#define AW_PID_1852_ADPI_DEFAULT		\
	(AW_PID_1852_ADPI_DEFAULT_VALUE << AW_PID_1852_ADPI_START_BIT)

/* BSTOCI bit 11 (SYSINT 0x02) */
#define AW_PID_1852_BSTOCI_START_BIT	(11)
#define AW_PID_1852_BSTOCI_BITS_LEN		(1)
#define AW_PID_1852_BSTOCI_MASK			\
	(~(((1<<AW_PID_1852_BSTOCI_BITS_LEN)-1) << AW_PID_1852_BSTOCI_START_BIT))

#define AW_PID_1852_BSTOCI_DEFAULT_VALUE	(0)
#define AW_PID_1852_BSTOCI_DEFAULT		\
	(AW_PID_1852_BSTOCI_DEFAULT_VALUE << AW_PID_1852_BSTOCI_START_BIT)

/* OVPI bit 10 (SYSINT 0x02) */
#define AW_PID_1852_OVPI_START_BIT		(10)
#define AW_PID_1852_OVPI_BITS_LEN		(1)
#define AW_PID_1852_OVPI_MASK			\
	(~(((1<<AW_PID_1852_OVPI_BITS_LEN)-1) << AW_PID_1852_OVPI_START_BIT))

#define AW_PID_1852_OVPI_DEFAULT_VALUE	(0)
#define AW_PID_1852_OVPI_DEFAULT		\
	(AW_PID_1852_OVPI_DEFAULT_VALUE << AW_PID_1852_OVPI_START_BIT)

/* BSTI bit 9 (SYSINT 0x02) */
#define AW_PID_1852_BSTI_START_BIT		(9)
#define AW_PID_1852_BSTI_BITS_LEN		(1)
#define AW_PID_1852_BSTI_MASK			\
	(~(((1<<AW_PID_1852_BSTI_BITS_LEN)-1) << AW_PID_1852_BSTI_START_BIT))

#define AW_PID_1852_BSTI_DEFAULT_VALUE	(0)
#define AW_PID_1852_BSTI_DEFAULT		\
	(AW_PID_1852_BSTI_DEFAULT_VALUE << AW_PID_1852_BSTI_START_BIT)

/* SWI bit 8 (SYSINT 0x02) */
#define AW_PID_1852_SWI_START_BIT		(8)
#define AW_PID_1852_SWI_BITS_LEN		(1)
#define AW_PID_1852_SWI_MASK			\
	(~(((1<<AW_PID_1852_SWI_BITS_LEN)-1) << AW_PID_1852_SWI_START_BIT))

#define AW_PID_1852_SWI_DEFAULT_VALUE	(0)
#define AW_PID_1852_SWI_DEFAULT			\
	(AW_PID_1852_SWI_DEFAULT_VALUE << AW_PID_1852_SWI_START_BIT)

/* CLIPI bit 7 (SYSINT 0x02) */
#define AW_PID_1852_CLIPI_START_BIT		(7)
#define AW_PID_1852_CLIPI_BITS_LEN		(1)
#define AW_PID_1852_CLIPI_MASK			\
	(~(((1<<AW_PID_1852_CLIPI_BITS_LEN)-1) << AW_PID_1852_CLIPI_START_BIT))

#define AW_PID_1852_CLIPI_DEFAULT_VALUE	(0)
#define AW_PID_1852_CLIPI_DEFAULT		\
	(AW_PID_1852_CLIPI_DEFAULT_VALUE << AW_PID_1852_CLIPI_START_BIT)

/* NOCLKI bit 5 (SYSINT 0x02) */
#define AW_PID_1852_NOCLKI_START_BIT	(5)
#define AW_PID_1852_NOCLKI_BITS_LEN		(1)
#define AW_PID_1852_NOCLKI_MASK			\
	(~(((1<<AW_PID_1852_NOCLKI_BITS_LEN)-1) << AW_PID_1852_NOCLKI_START_BIT))

#define AW_PID_1852_NOCLKI_DEFAULT_VALUE	(0)
#define AW_PID_1852_NOCLKI_DEFAULT		\
	(AW_PID_1852_NOCLKI_DEFAULT_VALUE << AW_PID_1852_NOCLKI_START_BIT)

/* CLKI bit 4 (SYSINT 0x02) */
#define AW_PID_1852_CLKI_START_BIT		(4)
#define AW_PID_1852_CLKI_BITS_LEN		(1)
#define AW_PID_1852_CLKI_MASK			\
	(~(((1<<AW_PID_1852_CLKI_BITS_LEN)-1) << AW_PID_1852_CLKI_START_BIT))

#define AW_PID_1852_CLKI_DEFAULT_VALUE	(0)
#define AW_PID_1852_CLKI_DEFAULT		\
	(AW_PID_1852_CLKI_DEFAULT_VALUE << AW_PID_1852_CLKI_START_BIT)

/* OCDI bit 3 (SYSINT 0x02) */
#define AW_PID_1852_OCDI_START_BIT		(3)
#define AW_PID_1852_OCDI_BITS_LEN		(1)
#define AW_PID_1852_OCDI_MASK			\
	(~(((1<<AW_PID_1852_OCDI_BITS_LEN)-1) << AW_PID_1852_OCDI_START_BIT))

#define AW_PID_1852_OCDI_DEFAULT_VALUE	(0)
#define AW_PID_1852_OCDI_DEFAULT		\
	(AW_PID_1852_OCDI_DEFAULT_VALUE << AW_PID_1852_OCDI_START_BIT)

/* CLIP_PREI bit 2 (SYSINT 0x02) */
#define AW_PID_1852_CLIP_PREI_START_BIT	(2)
#define AW_PID_1852_CLIP_PREI_BITS_LEN	(1)
#define AW_PID_1852_CLIP_PREI_MASK		\
	(~(((1<<AW_PID_1852_CLIP_PREI_BITS_LEN)-1) << AW_PID_1852_CLIP_PREI_START_BIT))

#define AW_PID_1852_CLIP_PREI_DEFAULT_VALUE	(0)
#define AW_PID_1852_CLIP_PREI_DEFAULT	\
	(AW_PID_1852_CLIP_PREI_DEFAULT_VALUE << AW_PID_1852_CLIP_PREI_START_BIT)

/* OTHI bit 1 (SYSINT 0x02) */
#define AW_PID_1852_OTHI_START_BIT		(1)
#define AW_PID_1852_OTHI_BITS_LEN		(1)
#define AW_PID_1852_OTHI_MASK			\
	(~(((1<<AW_PID_1852_OTHI_BITS_LEN)-1) << AW_PID_1852_OTHI_START_BIT))

#define AW_PID_1852_OTHI_DEFAULT_VALUE	(0)
#define AW_PID_1852_OTHI_DEFAULT		\
	(AW_PID_1852_OTHI_DEFAULT_VALUE << AW_PID_1852_OTHI_START_BIT)

/* PLLI bit 0 (SYSINT 0x02) */
#define AW_PID_1852_PLLI_START_BIT		(0)
#define AW_PID_1852_PLLI_BITS_LEN		(1)
#define AW_PID_1852_PLLI_MASK			\
	(~(((1<<AW_PID_1852_PLLI_BITS_LEN)-1) << AW_PID_1852_PLLI_START_BIT))

#define AW_PID_1852_PLLI_DEFAULT_VALUE	(0)
#define AW_PID_1852_PLLI_DEFAULT		\
	(AW_PID_1852_PLLI_DEFAULT_VALUE << AW_PID_1852_PLLI_START_BIT)

/* default value of SYSINT (0x02) */
/* #define AW_PID_1852_SYSINT_DEFAULT		(0x0000) */

/* SYSINTM (0x03) detail */
/* OVP2M bit 15 (SYSINTM 0x03) */
#define AW_PID_1852_OVP2M_START_BIT		(15)
#define AW_PID_1852_OVP2M_BITS_LEN		(1)
#define AW_PID_1852_OVP2M_MASK			\
	(~(((1<<AW_PID_1852_OVP2M_BITS_LEN)-1) << AW_PID_1852_OVP2M_START_BIT))

#define AW_PID_1852_OVP2M_DEFAULT_VALUE	(1)
#define AW_PID_1852_OVP2M_DEFAULT		\
	(AW_PID_1852_OVP2M_DEFAULT_VALUE << AW_PID_1852_OVP2M_START_BIT)

/* UVLM bit 14 (SYSINTM 0x03) */
#define AW_PID_1852_UVLM_START_BIT		(14)
#define AW_PID_1852_UVLM_BITS_LEN		(1)
#define AW_PID_1852_UVLM_MASK			\
	(~(((1<<AW_PID_1852_UVLM_BITS_LEN)-1) << AW_PID_1852_UVLM_START_BIT))

#define AW_PID_1852_UVLM_DEFAULT_VALUE	(1)
#define AW_PID_1852_UVLM_DEFAULT		\
	(AW_PID_1852_UVLM_DEFAULT_VALUE << AW_PID_1852_UVLM_START_BIT)

/* ADPM bit 13 (SYSINTM 0x03) */
#define AW_PID_1852_ADPM_START_BIT		(13)
#define AW_PID_1852_ADPM_BITS_LEN		(1)
#define AW_PID_1852_ADPM_MASK			\
	(~(((1<<AW_PID_1852_ADPM_BITS_LEN)-1) << AW_PID_1852_ADPM_START_BIT))

#define AW_PID_1852_ADPM_DEFAULT_VALUE	(1)
#define AW_PID_1852_ADPM_DEFAULT		\
	(AW_PID_1852_ADPM_DEFAULT_VALUE << AW_PID_1852_ADPM_START_BIT)

/* BSTOCM bit 11 (SYSINTM 0x03) */
#define AW_PID_1852_BSTOCM_START_BIT	(11)
#define AW_PID_1852_BSTOCM_BITS_LEN		(1)
#define AW_PID_1852_BSTOCM_MASK			\
	(~(((1<<AW_PID_1852_BSTOCM_BITS_LEN)-1) << AW_PID_1852_BSTOCM_START_BIT))

#define AW_PID_1852_BSTOCM_DEFAULT_VALUE	(1)
#define AW_PID_1852_BSTOCM_DEFAULT		\
	(AW_PID_1852_BSTOCM_DEFAULT_VALUE << AW_PID_1852_BSTOCM_START_BIT)

/* OVPM bit 10 (SYSINTM 0x03) */
#define AW_PID_1852_OVPM_START_BIT		(10)
#define AW_PID_1852_OVPM_BITS_LEN		(1)
#define AW_PID_1852_OVPM_MASK			\
	(~(((1<<AW_PID_1852_OVPM_BITS_LEN)-1) << AW_PID_1852_OVPM_START_BIT))

#define AW_PID_1852_OVPM_DEFAULT_VALUE	(1)
#define AW_PID_1852_OVPM_DEFAULT		\
	(AW_PID_1852_OVPM_DEFAULT_VALUE << AW_PID_1852_OVPM_START_BIT)

/* BSTM bit 9 (SYSINTM 0x03) */
#define AW_PID_1852_BSTM_START_BIT		(9)
#define AW_PID_1852_BSTM_BITS_LEN		(1)
#define AW_PID_1852_BSTM_MASK			\
	(~(((1<<AW_PID_1852_BSTM_BITS_LEN)-1) << AW_PID_1852_BSTM_START_BIT))

#define AW_PID_1852_BSTM_DEFAULT_VALUE	(1)
#define AW_PID_1852_BSTM_DEFAULT		\
	(AW_PID_1852_BSTM_DEFAULT_VALUE << AW_PID_1852_BSTM_START_BIT)

/* SWM bit 8 (SYSINTM 0x03) */
#define AW_PID_1852_SWM_START_BIT		(8)
#define AW_PID_1852_SWM_BITS_LEN		(1)
#define AW_PID_1852_SWM_MASK			\
	(~(((1<<AW_PID_1852_SWM_BITS_LEN)-1) << AW_PID_1852_SWM_START_BIT))

#define AW_PID_1852_SWM_DEFAULT_VALUE	(1)
#define AW_PID_1852_SWM_DEFAULT			\
	(AW_PID_1852_SWM_DEFAULT_VALUE << AW_PID_1852_SWM_START_BIT)

/* CLIPM bit 7 (SYSINTM 0x03) */
#define AW_PID_1852_CLIPM_START_BIT		(7)
#define AW_PID_1852_CLIPM_BITS_LEN		(1)
#define AW_PID_1852_CLIPM_MASK			\
	(~(((1<<AW_PID_1852_CLIPM_BITS_LEN)-1) << AW_PID_1852_CLIPM_START_BIT))

#define AW_PID_1852_CLIPM_DEFAULT_VALUE	(1)
#define AW_PID_1852_CLIPM_DEFAULT		\
	(AW_PID_1852_CLIPM_DEFAULT_VALUE << AW_PID_1852_CLIPM_START_BIT)

/* NOCLKM bit 5 (SYSINTM 0x03) */
#define AW_PID_1852_NOCLKM_START_BIT	(5)
#define AW_PID_1852_NOCLKM_BITS_LEN		(1)
#define AW_PID_1852_NOCLKM_MASK			\
	(~(((1<<AW_PID_1852_NOCLKM_BITS_LEN)-1) << AW_PID_1852_NOCLKM_START_BIT))

#define AW_PID_1852_NOCLKM_DEFAULT_VALUE	(1)
#define AW_PID_1852_NOCLKM_DEFAULT		\
	(AW_PID_1852_NOCLKM_DEFAULT_VALUE << AW_PID_1852_NOCLKM_START_BIT)

/* CLKM bit 4 (SYSINTM 0x03) */
#define AW_PID_1852_CLKM_START_BIT		(4)
#define AW_PID_1852_CLKM_BITS_LEN		(1)
#define AW_PID_1852_CLKM_MASK			\
	(~(((1<<AW_PID_1852_CLKM_BITS_LEN)-1) << AW_PID_1852_CLKM_START_BIT))

#define AW_PID_1852_CLKM_DEFAULT_VALUE	(1)
#define AW_PID_1852_CLKM_DEFAULT		\
	(AW_PID_1852_CLKM_DEFAULT_VALUE << AW_PID_1852_CLKM_START_BIT)

/* OCDM bit 3 (SYSINTM 0x03) */
#define AW_PID_1852_OCDM_START_BIT		(3)
#define AW_PID_1852_OCDM_BITS_LEN		(1)
#define AW_PID_1852_OCDM_MASK			\
	(~(((1<<AW_PID_1852_OCDM_BITS_LEN)-1) << AW_PID_1852_OCDM_START_BIT))

#define AW_PID_1852_OCDM_DEFAULT_VALUE	(1)
#define AW_PID_1852_OCDM_DEFAULT		\
	(AW_PID_1852_OCDM_DEFAULT_VALUE << AW_PID_1852_OCDM_START_BIT)

/* CLIP_PREM bit 2 (SYSINTM 0x03) */
#define AW_PID_1852_CLIP_PREM_START_BIT	(2)
#define AW_PID_1852_CLIP_PREM_BITS_LEN	(1)
#define AW_PID_1852_CLIP_PREM_MASK		\
	(~(((1<<AW_PID_1852_CLIP_PREM_BITS_LEN)-1) << AW_PID_1852_CLIP_PREM_START_BIT))

#define AW_PID_1852_CLIP_PREM_DEFAULT_VALUE	(1)
#define AW_PID_1852_CLIP_PREM_DEFAULT	\
	(AW_PID_1852_CLIP_PREM_DEFAULT_VALUE << AW_PID_1852_CLIP_PREM_START_BIT)

/* OTHM bit 1 (SYSINTM 0x03) */
#define AW_PID_1852_OTHM_START_BIT		(1)
#define AW_PID_1852_OTHM_BITS_LEN		(1)
#define AW_PID_1852_OTHM_MASK			\
	(~(((1<<AW_PID_1852_OTHM_BITS_LEN)-1) << AW_PID_1852_OTHM_START_BIT))

#define AW_PID_1852_OTHM_DEFAULT_VALUE	(1)
#define AW_PID_1852_OTHM_DEFAULT		\
	(AW_PID_1852_OTHM_DEFAULT_VALUE << AW_PID_1852_OTHM_START_BIT)

/* PLLM bit 0 (SYSINTM 0x03) */
#define AW_PID_1852_PLLM_START_BIT		(0)
#define AW_PID_1852_PLLM_BITS_LEN		(1)
#define AW_PID_1852_PLLM_MASK			\
	(~(((1<<AW_PID_1852_PLLM_BITS_LEN)-1) << AW_PID_1852_PLLM_START_BIT))

#define AW_PID_1852_PLLM_DEFAULT_VALUE	(1)
#define AW_PID_1852_PLLM_DEFAULT		\
	(AW_PID_1852_PLLM_DEFAULT_VALUE << AW_PID_1852_PLLM_START_BIT)

/* default value of SYSINTM (0x03) */
#define  AW_PID_1852_SYSINTM_DEFAULT		(0xEFBF)

/* SYSCTRL (0x04) detail */
/* SPK_GAIN bit 14:12 (SYSCTRL 0x04) */
#define AW_PID_1852_SPK_GAIN_START_BIT	(12)
#define AW_PID_1852_SPK_GAIN_BITS_LEN	(3)
#define AW_PID_1852_SPK_GAIN_MASK		\
	(~(((1<<AW_PID_1852_SPK_GAIN_BITS_LEN)-1) << AW_PID_1852_SPK_GAIN_START_BIT))

#define AW_PID_1852_SPK_GAIN_AV7		(0)
#define AW_PID_1852_SPK_GAIN_AV7_VALUE	\
	(AW_PID_1852_SPK_GAIN_AV7 << AW_PID_1852_SPK_GAIN_START_BIT)

#define AW_PID_1852_SPK_GAIN_AV8		(1)
#define AW_PID_1852_SPK_GAIN_AV8_VALUE	\
	(AW_PID_1852_SPK_GAIN_AV8 << AW_PID_1852_SPK_GAIN_START_BIT)

#define AW_PID_1852_SPK_GAIN_AV10		(2)
#define AW_PID_1852_SPK_GAIN_AV10_VALUE	\
	(AW_PID_1852_SPK_GAIN_AV10 << AW_PID_1852_SPK_GAIN_START_BIT)

#define AW_PID_1852_SPK_GAIN_AV14		(3)
#define AW_PID_1852_SPK_GAIN_AV14_VALUE	\
	(AW_PID_1852_SPK_GAIN_AV14 << AW_PID_1852_SPK_GAIN_START_BIT)

#define AW_PID_1852_SPK_GAIN_AV16		(4)
#define AW_PID_1852_SPK_GAIN_AV16_VALUE	\
	(AW_PID_1852_SPK_GAIN_AV16 << AW_PID_1852_SPK_GAIN_START_BIT)

#define AW_PID_1852_SPK_GAIN_AV20		(5)
#define AW_PID_1852_SPK_GAIN_AV20_VALUE	\
	(AW_PID_1852_SPK_GAIN_AV20 << AW_PID_1852_SPK_GAIN_START_BIT)

#define AW_PID_1852_SPK_GAIN_DEFAULT_VALUE	(0x4)
#define AW_PID_1852_SPK_GAIN_DEFAULT	\
	(AW_PID_1852_SPK_GAIN_DEFAULT_VALUE << AW_PID_1852_SPK_GAIN_START_BIT)

/* RCV_GAIN bit 11:10 (SYSCTRL 0x04) */
#define AW_PID_1852_RCV_GAIN_START_BIT	(10)
#define AW_PID_1852_RCV_GAIN_BITS_LEN	(2)
#define AW_PID_1852_RCV_GAIN_MASK		\
	(~(((1<<AW_PID_1852_RCV_GAIN_BITS_LEN)-1) << AW_PID_1852_RCV_GAIN_START_BIT))

#define AW_PID_1852_RCV_GAIN_AV4P5		(0)
#define AW_PID_1852_RCV_GAIN_AV4P5_VALUE	\
	(AW_PID_1852_RCV_GAIN_AV4P5 << AW_PID_1852_RCV_GAIN_START_BIT)

#define AW_PID_1852_RCV_GAIN_AV5		(1)
#define AW_PID_1852_RCV_GAIN_AV5_VALUE	\
	(AW_PID_1852_RCV_GAIN_AV5 << AW_PID_1852_RCV_GAIN_START_BIT)

#define AW_PID_1852_RCV_GAIN_AV5P5		(2)
#define AW_PID_1852_RCV_GAIN_AV5P5_VALUE	\
	(AW_PID_1852_RCV_GAIN_AV5P5 << AW_PID_1852_RCV_GAIN_START_BIT)

#define AW_PID_1852_RCV_GAIN_AV7P5		(3)
#define AW_PID_1852_RCV_GAIN_AV7P5_VALUE	\
	(AW_PID_1852_RCV_GAIN_AV7P5 << AW_PID_1852_RCV_GAIN_START_BIT)

#define AW_PID_1852_RCV_GAIN_DEFAULT_VALUE	(0)
#define AW_PID_1852_RCV_GAIN_DEFAULT	\
	(AW_PID_1852_RCV_GAIN_DEFAULT_VALUE << AW_PID_1852_RCV_GAIN_START_BIT)

/* INTMODE bit 9 (SYSCTRL 0x04) */
#define AW_PID_1852_INTMODE_START_BIT	(9)
#define AW_PID_1852_INTMODE_BITS_LEN	(1)
#define AW_PID_1852_INTMODE_MASK		\
	(~(((1<<AW_PID_1852_INTMODE_BITS_LEN)-1) << AW_PID_1852_INTMODE_START_BIT))

#define AW_PID_1852_INTMODE_OPENMINUS_DRAIN	(0)
#define AW_PID_1852_INTMODE_OPENMINUS_DRAIN_VALUE	\
	(AW_PID_1852_INTMODE_OPENMINUS_DRAIN << AW_PID_1852_INTMODE_START_BIT)

#define AW_PID_1852_INTMODE_PUSHPULL	(1)
#define AW_PID_1852_INTMODE_PUSHPULL_VALUE	\
	(AW_PID_1852_INTMODE_PUSHPULL << AW_PID_1852_INTMODE_START_BIT)

#define AW_PID_1852_INTMODE_DEFAULT_VALUE	(0)
#define AW_PID_1852_INTMODE_DEFAULT		\
	(AW_PID_1852_INTMODE_DEFAULT_VALUE << AW_PID_1852_INTMODE_START_BIT)

/* INTN bit 8 (SYSCTRL 0x04) */
#define AW_PID_1852_INTN_START_BIT		(8)
#define AW_PID_1852_INTN_BITS_LEN		(1)
#define AW_PID_1852_INTN_MASK			\
	(~(((1<<AW_PID_1852_INTN_BITS_LEN)-1) << AW_PID_1852_INTN_START_BIT))

#define AW_PID_1852_INTN_SYSINT			(0)
#define AW_PID_1852_INTN_SYSINT_VALUE	\
	(AW_PID_1852_INTN_SYSINT << AW_PID_1852_INTN_START_BIT)

#define AW_PID_1852_INTN_SYSST			(1)
#define AW_PID_1852_INTN_SYSST_VALUE	\
	(AW_PID_1852_INTN_SYSST << AW_PID_1852_INTN_START_BIT)

#define AW_PID_1852_INTN_DEFAULT_VALUE	(0)
#define AW_PID_1852_INTN_DEFAULT		\
	(AW_PID_1852_INTN_DEFAULT_VALUE << AW_PID_1852_INTN_START_BIT)

/* RCV_MODE bit 7 (SYSCTRL 0x04) */
#define AW_PID_1852_RCV_MODE_START_BIT	(7)
#define AW_PID_1852_RCV_MODE_BITS_LEN	(1)
#define AW_PID_1852_RCV_MODE_MASK		\
	(~(((1<<AW_PID_1852_RCV_MODE_BITS_LEN)-1) << AW_PID_1852_RCV_MODE_START_BIT))

#define AW_PID_1852_RCV_MODE_SPEAKER_MODE_VCOM13PVDD	(0)
#define AW_PID_1852_RCV_MODE_SPEAKER_MODE_VCOM13PVDD_VALUE	\
	(AW_PID_1852_RCV_MODE_SPEAKER_MODE_VCOM13PVDD << AW_PID_1852_RCV_MODE_START_BIT)

#define AW_PID_1852_RCV_MODE_RECEIVER_MODE_VCOM12PVDD	(1)
#define AW_PID_1852_RCV_MODE_RECEIVER_MODE_VCOM12PVDD_VALUE	\
	(AW_PID_1852_RCV_MODE_RECEIVER_MODE_VCOM12PVDD << AW_PID_1852_RCV_MODE_START_BIT)

#define AW_PID_1852_RCV_MODE_DEFAULT_VALUE	(0)
#define AW_PID_1852_RCV_MODE_DEFAULT	\
	(AW_PID_1852_RCV_MODE_DEFAULT_VALUE << AW_PID_1852_RCV_MODE_START_BIT)

/* I2SEN bit 6 (SYSCTRL 0x04) */
#define AW_PID_1852_I2SEN_START_BIT		(6)
#define AW_PID_1852_I2SEN_BITS_LEN		(1)
#define AW_PID_1852_I2SEN_MASK			\
	(~(((1<<AW_PID_1852_I2SEN_BITS_LEN)-1) << AW_PID_1852_I2SEN_START_BIT))

#define AW_PID_1852_I2SEN_DISABLE		(0)
#define AW_PID_1852_I2SEN_DISABLE_VALUE	\
	(AW_PID_1852_I2SEN_DISABLE << AW_PID_1852_I2SEN_START_BIT)

#define AW_PID_1852_I2SEN_ENABLE		(1)
#define AW_PID_1852_I2SEN_ENABLE_VALUE	\
	(AW_PID_1852_I2SEN_ENABLE << AW_PID_1852_I2SEN_START_BIT)

#define AW_PID_1852_I2SEN_DEFAULT_VALUE	(0)
#define AW_PID_1852_I2SEN_DEFAULT		\
	(AW_PID_1852_I2SEN_DEFAULT_VALUE << AW_PID_1852_I2SEN_START_BIT)

/* WSINV bit 5 (SYSCTRL 0x04) */
#define AW_PID_1852_WSINV_START_BIT		(5)
#define AW_PID_1852_WSINV_BITS_LEN		(1)
#define AW_PID_1852_WSINV_MASK			\
	(~(((1<<AW_PID_1852_WSINV_BITS_LEN)-1) << AW_PID_1852_WSINV_START_BIT))

#define AW_PID_1852_WSINV_NO_SWITCH		(0)
#define AW_PID_1852_WSINV_NO_SWITCH_VALUE	\
	(AW_PID_1852_WSINV_NO_SWITCH << AW_PID_1852_WSINV_START_BIT)

#define AW_PID_1852_WSINV_LEFTRIGHT_SWITCH	(1)
#define AW_PID_1852_WSINV_LEFTRIGHT_SWITCH_VALUE	\
	(AW_PID_1852_WSINV_LEFTRIGHT_SWITCH << AW_PID_1852_WSINV_START_BIT)

#define AW_PID_1852_WSINV_DEFAULT_VALUE	(0)
#define AW_PID_1852_WSINV_DEFAULT		\
	(AW_PID_1852_WSINV_DEFAULT_VALUE << AW_PID_1852_WSINV_START_BIT)

/* BCKINV bit 4 (SYSCTRL 0x04) */
#define AW_PID_1852_BCKINV_START_BIT	(4)
#define AW_PID_1852_BCKINV_BITS_LEN		(1)
#define AW_PID_1852_BCKINV_MASK			\
	(~(((1<<AW_PID_1852_BCKINV_BITS_LEN)-1) << AW_PID_1852_BCKINV_START_BIT))

#define AW_PID_1852_BCKINV_NOT_INVERT	(0)
#define AW_PID_1852_BCKINV_NOT_INVERT_VALUE	\
	(AW_PID_1852_BCKINV_NOT_INVERT << AW_PID_1852_BCKINV_START_BIT)

#define AW_PID_1852_BCKINV_INVERTED		(1)
#define AW_PID_1852_BCKINV_INVERTED_VALUE	\
	(AW_PID_1852_BCKINV_INVERTED << AW_PID_1852_BCKINV_START_BIT)

#define AW_PID_1852_BCKINV_DEFAULT_VALUE	(0)
#define AW_PID_1852_BCKINV_DEFAULT		\
	(AW_PID_1852_BCKINV_DEFAULT_VALUE << AW_PID_1852_BCKINV_START_BIT)

/* IPLL bit 3 (SYSCTRL 0x04) */
#define AW_PID_1852_IPLL_START_BIT		(3)
#define AW_PID_1852_IPLL_BITS_LEN		(1)
#define AW_PID_1852_IPLL_MASK			\
	(~(((1<<AW_PID_1852_IPLL_BITS_LEN)-1) << AW_PID_1852_IPLL_START_BIT))

#define AW_PID_1852_IPLL_BIT_CLOCK		(0)
#define AW_PID_1852_IPLL_BIT_CLOCK_VALUE	\
	(AW_PID_1852_IPLL_BIT_CLOCK << AW_PID_1852_IPLL_START_BIT)

#define AW_PID_1852_IPLL_WORD_SELECTION_SIGNAL	(1)
#define AW_PID_1852_IPLL_WORD_SELECTION_SIGNAL_VALUE	\
	(AW_PID_1852_IPLL_WORD_SELECTION_SIGNAL << AW_PID_1852_IPLL_START_BIT)

#define AW_PID_1852_IPLL_DEFAULT_VALUE	(0)
#define AW_PID_1852_IPLL_DEFAULT		\
	(AW_PID_1852_IPLL_DEFAULT_VALUE << AW_PID_1852_IPLL_START_BIT)

/* AMPPD bit 1 (SYSCTRL 0x04) */
#define AW_PID_1852_AMPPD_START_BIT		(1)
#define AW_PID_1852_AMPPD_BITS_LEN		(1)
#define AW_PID_1852_AMPPD_MASK			\
	(~(((1<<AW_PID_1852_AMPPD_BITS_LEN)-1) << AW_PID_1852_AMPPD_START_BIT))

#define AW_PID_1852_AMPPD_NORMAL_WORKING	(0)
#define AW_PID_1852_AMPPD_NORMAL_WORKING_VALUE	\
	(AW_PID_1852_AMPPD_NORMAL_WORKING << AW_PID_1852_AMPPD_START_BIT)

#define AW_PID_1852_AMPPD_POWER_DOWN	(1)
#define AW_PID_1852_AMPPD_POWER_DOWN_VALUE	\
	(AW_PID_1852_AMPPD_POWER_DOWN << AW_PID_1852_AMPPD_START_BIT)

#define AW_PID_1852_AMPPD_DEFAULT_VALUE	(1)
#define AW_PID_1852_AMPPD_DEFAULT		\
	(AW_PID_1852_AMPPD_DEFAULT_VALUE << AW_PID_1852_AMPPD_START_BIT)

/* PWDN bit 0 (SYSCTRL 0x04) */
#define AW_PID_1852_PWDN_START_BIT			(0)
#define AW_PID_1852_PWDN_BITS_LEN			(1)
#define AW_PID_1852_PWDN_MASK				\
	(~(((1<<AW_PID_1852_PWDN_BITS_LEN)-1)<<AW_PID_1852_PWDN_START_BIT))

#define AW_PID_1852_PWDN_NORMAL_WORKING		(0)
#define AW_PID_1852_PWDN_NORMAL_WORKING_VALUE	\
	(AW_PID_1852_PWDN_NORMAL_WORKING << AW_PID_1852_PWDN_START_BIT)
#define AW_PID_1852_PWDN_POWER_DOWN			(1)
#define AW_PID_1852_PWDN_POWER_DOWN_VALUE	\
	(AW_PID_1852_PWDN_POWER_DOWN << AW_PID_1852_PWDN_START_BIT)

#define AW_PID_1852_PWDN_DEFAULT_VALUE		(1)
#define AW_PID_1852_PWDN_DEFAULT			\
	(AW_PID_1852_PWDN_DEFAULT_VALUE<<AW_PID_1852_PWDN_START_BIT)

/* default value of SYSCTRL (0x04) */
/* #define AW_PID_1852_SYSCTRL_DEFAULT		(0x4003) */

/* SYSCTRL2 (0x05) detail */
/* RMSE bit 7 (SYSCTRL2 0x05) */
#define AW_PID_1852_RMSE_START_BIT		(7)
#define AW_PID_1852_RMSE_BITS_LEN		(1)
#define AW_PID_1852_RMSE_MASK			\
	(~(((1<<AW_PID_1852_RMSE_BITS_LEN)-1) << AW_PID_1852_RMSE_START_BIT))

#define AW_PID_1852_RMSE_DISABLE		(0)
#define AW_PID_1852_RMSE_DISABLE_VALUE	\
	(AW_PID_1852_RMSE_DISABLE << AW_PID_1852_RMSE_START_BIT)

#define AW_PID_1852_RMSE_ENABLE			(1)
#define AW_PID_1852_RMSE_ENABLE_VALUE	\
	(AW_PID_1852_RMSE_ENABLE << AW_PID_1852_RMSE_START_BIT)

#define AW_PID_1852_RMSE_DEFAULT_VALUE	(0)
#define AW_PID_1852_RMSE_DEFAULT		\
	(AW_PID_1852_RMSE_DEFAULT_VALUE << AW_PID_1852_RMSE_START_BIT)

/* HAGCE bit 6 (SYSCTRL2 0x05) */
#define AW_PID_1852_HAGCE_START_BIT		(6)
#define AW_PID_1852_HAGCE_BITS_LEN		(1)
#define AW_PID_1852_HAGCE_MASK			\
	(~(((1<<AW_PID_1852_HAGCE_BITS_LEN)-1) << AW_PID_1852_HAGCE_START_BIT))

#define AW_PID_1852_HAGCE_DISABLE		(0)
#define AW_PID_1852_HAGCE_DISABLE_VALUE	\
	(AW_PID_1852_HAGCE_DISABLE << AW_PID_1852_HAGCE_START_BIT)

#define AW_PID_1852_HAGCE_ENABLE		(1)
#define AW_PID_1852_HAGCE_ENABLE_VALUE	\
	(AW_PID_1852_HAGCE_ENABLE << AW_PID_1852_HAGCE_START_BIT)

#define AW_PID_1852_HAGCE_DEFAULT_VALUE	(0)
#define AW_PID_1852_HAGCE_DEFAULT		\
	(AW_PID_1852_HAGCE_DEFAULT_VALUE << AW_PID_1852_HAGCE_START_BIT)

/* HDCCE bit 5 (SYSCTRL2 0x05) */
#define AW_PID_1852_HDCCE_START_BIT		(5)
#define AW_PID_1852_HDCCE_BITS_LEN		(1)
#define AW_PID_1852_HDCCE_MASK			\
	(~(((1<<AW_PID_1852_HDCCE_BITS_LEN)-1) << AW_PID_1852_HDCCE_START_BIT))

#define AW_PID_1852_HDCCE_DISABLE		(0)
#define AW_PID_1852_HDCCE_DISABLE_VALUE	\
	(AW_PID_1852_HDCCE_DISABLE << AW_PID_1852_HDCCE_START_BIT)

#define AW_PID_1852_HDCCE_ENABLE		(1)
#define AW_PID_1852_HDCCE_ENABLE_VALUE	\
	(AW_PID_1852_HDCCE_ENABLE << AW_PID_1852_HDCCE_START_BIT)

#define AW_PID_1852_HDCCE_DEFAULT_VALUE	(1)
#define AW_PID_1852_HDCCE_DEFAULT		\
	(AW_PID_1852_HDCCE_DEFAULT_VALUE << AW_PID_1852_HDCCE_START_BIT)

/* HMUTE bit 4 (SYSCTRL2 0x05) */
#define AW_PID_1852_HMUTE_START_BIT		(4)
#define AW_PID_1852_HMUTE_BITS_LEN		(1)
#define AW_PID_1852_HMUTE_MASK			\
	(~(((1<<AW_PID_1852_HMUTE_BITS_LEN)-1) << AW_PID_1852_HMUTE_START_BIT))

#define AW_PID_1852_HMUTE_DISABLE		(0)
#define AW_PID_1852_HMUTE_DISABLE_VALUE	\
	(AW_PID_1852_HMUTE_DISABLE << AW_PID_1852_HMUTE_START_BIT)

#define AW_PID_1852_HMUTE_ENABLE		(1)
#define AW_PID_1852_HMUTE_ENABLE_VALUE	\
	(AW_PID_1852_HMUTE_ENABLE << AW_PID_1852_HMUTE_START_BIT)

#define AW_PID_1852_HMUTE_DEFAULT_VALUE	(1)
#define AW_PID_1852_HMUTE_DEFAULT		\
	(AW_PID_1852_HMUTE_DEFAULT_VALUE << AW_PID_1852_HMUTE_START_BIT)

/* BST_IPEAK bit 3:0 (SYSCTRL2 0x05) */
#define AW_PID_1852_BST_IPEAK_START_BIT	(0)
#define AW_PID_1852_BST_IPEAK_BITS_LEN	(4)
#define AW_PID_1852_BST_IPEAK_MASK		\
	(~(((1<<AW_PID_1852_BST_IPEAK_BITS_LEN)-1) << AW_PID_1852_BST_IPEAK_START_BIT))

#define AW_PID_1852_BST_IPEAK_1P5A		(0)
#define AW_PID_1852_BST_IPEAK_1P5A_VALUE	\
	(AW_PID_1852_BST_IPEAK_1P5A << AW_PID_1852_BST_IPEAK_START_BIT)

#define AW_PID_1852_BST_IPEAK_1P75A		(1)
#define AW_PID_1852_BST_IPEAK_1P75A_VALUE	\
	(AW_PID_1852_BST_IPEAK_1P75A << AW_PID_1852_BST_IPEAK_START_BIT)

#define AW_PID_1852_BST_IPEAK_2P0A		(2)
#define AW_PID_1852_BST_IPEAK_2P0A_VALUE	\
	(AW_PID_1852_BST_IPEAK_2P0A << AW_PID_1852_BST_IPEAK_START_BIT)

#define AW_PID_1852_BST_IPEAK_2P25A		(3)
#define AW_PID_1852_BST_IPEAK_2P25A_VALUE	\
	(AW_PID_1852_BST_IPEAK_2P25A << AW_PID_1852_BST_IPEAK_START_BIT)

#define AW_PID_1852_BST_IPEAK_2P5A		(4)
#define AW_PID_1852_BST_IPEAK_2P5A_VALUE	\
	(AW_PID_1852_BST_IPEAK_2P5A << AW_PID_1852_BST_IPEAK_START_BIT)

#define AW_PID_1852_BST_IPEAK_2P75A		(5)
#define AW_PID_1852_BST_IPEAK_2P75A_VALUE	\
	(AW_PID_1852_BST_IPEAK_2P75A << AW_PID_1852_BST_IPEAK_START_BIT)

#define AW_PID_1852_BST_IPEAK_3P0A		(6)
#define AW_PID_1852_BST_IPEAK_3P0A_VALUE	\
	(AW_PID_1852_BST_IPEAK_3P0A << AW_PID_1852_BST_IPEAK_START_BIT)

#define AW_PID_1852_BST_IPEAK_3P25A		(7)
#define AW_PID_1852_BST_IPEAK_3P25A_VALUE	\
	(AW_PID_1852_BST_IPEAK_3P25A << AW_PID_1852_BST_IPEAK_START_BIT)

#define AW_PID_1852_BST_IPEAK_3P5A		(8)
#define AW_PID_1852_BST_IPEAK_3P5A_VALUE	\
	(AW_PID_1852_BST_IPEAK_3P5A << AW_PID_1852_BST_IPEAK_START_BIT)

#define AW_PID_1852_BST_IPEAK_3P75A		(9)
#define AW_PID_1852_BST_IPEAK_3P75A_VALUE	\
	(AW_PID_1852_BST_IPEAK_3P75A << AW_PID_1852_BST_IPEAK_START_BIT)

#define AW_PID_1852_BST_IPEAK_4A		(10)
#define AW_PID_1852_BST_IPEAK_4A_VALUE	\
	(AW_PID_1852_BST_IPEAK_4A << AW_PID_1852_BST_IPEAK_START_BIT)

#define AW_PID_1852_BST_IPEAK_4P25A		(11)
#define AW_PID_1852_BST_IPEAK_4P25A_VALUE	\
	(AW_PID_1852_BST_IPEAK_4P25A << AW_PID_1852_BST_IPEAK_START_BIT)

#define AW_PID_1852_BST_IPEAK_DEFAULT_VALUE	(8)
#define AW_PID_1852_BST_IPEAK_DEFAULT	\
	(AW_PID_1852_BST_IPEAK_DEFAULT_VALUE << AW_PID_1852_BST_IPEAK_START_BIT)

/* default value of SYSCTRL2 (0x05) */
/* #define AW_PID_1852_SYSCTRL2_DEFAULT		(0x0038) */

/* I2SCTRL (0x06) detail */
/* INPLEV bit 13 (I2SCTRL 0x06) */
#define AW_PID_1852_INPLEV_START_BIT	(13)
#define AW_PID_1852_INPLEV_BITS_LEN		(1)
#define AW_PID_1852_INPLEV_MASK			\
	(~(((1<<AW_PID_1852_INPLEV_BITS_LEN)-1) << AW_PID_1852_INPLEV_START_BIT))

#define AW_PID_1852_INPLEV_NOT_ATTENUATED	(0)
#define AW_PID_1852_INPLEV_NOT_ATTENUATED_VALUE	\
	(AW_PID_1852_INPLEV_NOT_ATTENUATED << AW_PID_1852_INPLEV_START_BIT)

#define AW_PID_1852_INPLEV_ATTENUATED_BY_MINUS_6DB	(1)
#define AW_PID_1852_INPLEV_ATTENUATED_BY_MINUS_6DB_VALUE	\
	(AW_PID_1852_INPLEV_ATTENUATED_BY_MINUS_6DB << AW_PID_1852_INPLEV_START_BIT)

#define AW_PID_1852_INPLEV_DEFAULT_VALUE	(0)
#define AW_PID_1852_INPLEV_DEFAULT		\
	(AW_PID_1852_INPLEV_DEFAULT_VALUE << AW_PID_1852_INPLEV_START_BIT)

/* I2SRXEN bit 12 (I2SCTRL 0x06) */
#define AW_PID_1852_I2SRXEN_START_BIT	(12)
#define AW_PID_1852_I2SRXEN_BITS_LEN	(1)
#define AW_PID_1852_I2SRXEN_MASK		\
	(~(((1<<AW_PID_1852_I2SRXEN_BITS_LEN)-1) << AW_PID_1852_I2SRXEN_START_BIT))

#define AW_PID_1852_I2SRXEN_DISABLE		(0)
#define AW_PID_1852_I2SRXEN_DISABLE_VALUE	\
	(AW_PID_1852_I2SRXEN_DISABLE << AW_PID_1852_I2SRXEN_START_BIT)

#define AW_PID_1852_I2SRXEN_ENABLE		(1)
#define AW_PID_1852_I2SRXEN_ENABLE_VALUE	\
	(AW_PID_1852_I2SRXEN_ENABLE << AW_PID_1852_I2SRXEN_START_BIT)

#define AW_PID_1852_I2SRXEN_DEFAULT_VALUE	(1)
#define AW_PID_1852_I2SRXEN_DEFAULT		\
	(AW_PID_1852_I2SRXEN_DEFAULT_VALUE << AW_PID_1852_I2SRXEN_START_BIT)

/* CHSEL bit 11:10 (I2SCTRL 0x06) */
#define AW_PID_1852_CHSEL_START_BIT		(10)
#define AW_PID_1852_CHSEL_BITS_LEN		(2)
#define AW_PID_1852_CHSEL_MASK			\
	(~(((1<<AW_PID_1852_CHSEL_BITS_LEN)-1) << AW_PID_1852_CHSEL_START_BIT))

#define AW_PID_1852_CHSEL_RESERVED		(0)
#define AW_PID_1852_CHSEL_RESERVED_VALUE	\
	(AW_PID_1852_CHSEL_RESERVED << AW_PID_1852_CHSEL_START_BIT)

#define AW_PID_1852_CHSEL_LEFT			(1)
#define AW_PID_1852_CHSEL_LEFT_VALUE	\
	(AW_PID_1852_CHSEL_LEFT << AW_PID_1852_CHSEL_START_BIT)

#define AW_PID_1852_CHSEL_RIGHT			(2)
#define AW_PID_1852_CHSEL_RIGHT_VALUE	\
	(AW_PID_1852_CHSEL_RIGHT << AW_PID_1852_CHSEL_START_BIT)

#define AW_PID_1852_CHSEL_MONO_LR2		(3)
#define AW_PID_1852_CHSEL_MONO_LR2_VALUE	\
	(AW_PID_1852_CHSEL_MONO_LR2 << AW_PID_1852_CHSEL_START_BIT)

#define AW_PID_1852_CHSEL_DEFAULT_VALUE	(1)
#define AW_PID_1852_CHSEL_DEFAULT		\
	(AW_PID_1852_CHSEL_DEFAULT_VALUE << AW_PID_1852_CHSEL_START_BIT)

/* I2SMD bit 9:8 (I2SCTRL 0x06) */
#define AW_PID_1852_I2SMD_START_BIT		(8)
#define AW_PID_1852_I2SMD_BITS_LEN		(2)
#define AW_PID_1852_I2SMD_MASK			\
	(~(((1<<AW_PID_1852_I2SMD_BITS_LEN)-1) << AW_PID_1852_I2SMD_START_BIT))

#define AW_PID_1852_I2SMD_PHILIP_STANDARD_I2S_DEFAULT	(0)
#define AW_PID_1852_I2SMD_PHILIP_STANDARD_I2S_DEFAULT_VALUE	\
	(AW_PID_1852_I2SMD_PHILIP_STANDARD_I2S_DEFAULT << AW_PID_1852_I2SMD_START_BIT)

#define AW_PID_1852_I2SMD_MSB_JUSTIFIED	(1)
#define AW_PID_1852_I2SMD_MSB_JUSTIFIED_VALUE	\
	(AW_PID_1852_I2SMD_MSB_JUSTIFIED << AW_PID_1852_I2SMD_START_BIT)

#define AW_PID_1852_I2SMD_LSB_JUSTIFIED	(2)
#define AW_PID_1852_I2SMD_LSB_JUSTIFIED_VALUE	\
	(AW_PID_1852_I2SMD_LSB_JUSTIFIED << AW_PID_1852_I2SMD_START_BIT)

#define AW_PID_1852_I2SMD_RESERVED		(3)
#define AW_PID_1852_I2SMD_RESERVED_VALUE	\
	(AW_PID_1852_I2SMD_RESERVED << AW_PID_1852_I2SMD_START_BIT)

#define AW_PID_1852_I2SMD_DEFAULT_VALUE	(0)
#define AW_PID_1852_I2SMD_DEFAULT		\
	(AW_PID_1852_I2SMD_DEFAULT_VALUE << AW_PID_1852_I2SMD_START_BIT)

/* I2SFS bit 7:6 (I2SCTRL 0x06) */
#define AW_PID_1852_I2SFS_START_BIT		(6)
#define AW_PID_1852_I2SFS_BITS_LEN		(2)
#define AW_PID_1852_I2SFS_MASK			\
	(~(((1<<AW_PID_1852_I2SFS_BITS_LEN)-1) << AW_PID_1852_I2SFS_START_BIT))

#define AW_PID_1852_I2SFS_16_BITS		(0)
#define AW_PID_1852_I2SFS_16_BITS_VALUE	\
	(AW_PID_1852_I2SFS_16_BITS << AW_PID_1852_I2SFS_START_BIT)

#define AW_PID_1852_I2SFS_20_BITS		(1)
#define AW_PID_1852_I2SFS_20_BITS_VALUE	\
	(AW_PID_1852_I2SFS_20_BITS << AW_PID_1852_I2SFS_START_BIT)

#define AW_PID_1852_I2SFS_24_BITS		(2)
#define AW_PID_1852_I2SFS_24_BITS_VALUE	\
	(AW_PID_1852_I2SFS_24_BITS << AW_PID_1852_I2SFS_START_BIT)

#define AW_PID_1852_I2SFS_32_BITS		(3)
#define AW_PID_1852_I2SFS_32_BITS_VALUE	\
	(AW_PID_1852_I2SFS_32_BITS << AW_PID_1852_I2SFS_START_BIT)

#define AW_PID_1852_I2SFS_DEFAULT_VALUE	(3)
#define AW_PID_1852_I2SFS_DEFAULT		\
	(AW_PID_1852_I2SFS_DEFAULT_VALUE << AW_PID_1852_I2SFS_START_BIT)

/* I2SBCK bit 5:4 (I2SCTRL 0x06) */
#define AW_PID_1852_I2SBCK_START_BIT	(4)
#define AW_PID_1852_I2SBCK_BITS_LEN		(2)
#define AW_PID_1852_I2SBCK_MASK			\
	(~(((1<<AW_PID_1852_I2SBCK_BITS_LEN)-1) << AW_PID_1852_I2SBCK_START_BIT))

#define AW_PID_1852_I2SBCK_32FS162		(0)
#define AW_PID_1852_I2SBCK_32FS162_VALUE	\
	(AW_PID_1852_I2SBCK_32FS162 << AW_PID_1852_I2SBCK_START_BIT)

#define AW_PID_1852_I2SBCK_48FS242		(1)
#define AW_PID_1852_I2SBCK_48FS242_VALUE	\
	(AW_PID_1852_I2SBCK_48FS242 << AW_PID_1852_I2SBCK_START_BIT)

#define AW_PID_1852_I2SBCK_64FS322		(2)
#define AW_PID_1852_I2SBCK_64FS322_VALUE	\
	(AW_PID_1852_I2SBCK_64FS322 << AW_PID_1852_I2SBCK_START_BIT)

#define AW_PID_1852_I2SBCK_RESERVED		(3)
#define AW_PID_1852_I2SBCK_RESERVED_VALUE	\
	(AW_PID_1852_I2SBCK_RESERVED << AW_PID_1852_I2SBCK_START_BIT)

#define AW_PID_1852_I2SBCK_DEFAULT_VALUE	(2)
#define AW_PID_1852_I2SBCK_DEFAULT		\
	(AW_PID_1852_I2SBCK_DEFAULT_VALUE << AW_PID_1852_I2SBCK_START_BIT)

/* I2SSR bit 3:0 (I2SCTRL 0x06) */
#define AW_PID_1852_I2SSR_START_BIT		(0)
#define AW_PID_1852_I2SSR_BITS_LEN		(4)
#define AW_PID_1852_I2SSR_MASK			\
	(~(((1<<AW_PID_1852_I2SSR_BITS_LEN)-1) << AW_PID_1852_I2SSR_START_BIT))

#define AW_PID_1852_I2SSR_8_KHZ			(0)
#define AW_PID_1852_I2SSR_8_KHZ_VALUE	\
	(AW_PID_1852_I2SSR_8_KHZ << AW_PID_1852_I2SSR_START_BIT)

#define AW_PID_1852_I2SSR_11P025_KHZ	(1)
#define AW_PID_1852_I2SSR_11P025_KHZ_VALUE	\
	(AW_PID_1852_I2SSR_11P025_KHZ << AW_PID_1852_I2SSR_START_BIT)

#define AW_PID_1852_I2SSR_12_KHZ		(2)
#define AW_PID_1852_I2SSR_12_KHZ_VALUE	\
	(AW_PID_1852_I2SSR_12_KHZ << AW_PID_1852_I2SSR_START_BIT)

#define AW_PID_1852_I2SSR_16_KHZ		(3)
#define AW_PID_1852_I2SSR_16_KHZ_VALUE	\
	(AW_PID_1852_I2SSR_16_KHZ << AW_PID_1852_I2SSR_START_BIT)

#define AW_PID_1852_I2SSR_22P05KHZ		(4)
#define AW_PID_1852_I2SSR_22P05KHZ_VALUE	\
	(AW_PID_1852_I2SSR_22P05KHZ << AW_PID_1852_I2SSR_START_BIT)

#define AW_PID_1852_I2SSR_24_KHZ		(5)
#define AW_PID_1852_I2SSR_24_KHZ_VALUE	\
	(AW_PID_1852_I2SSR_24_KHZ << AW_PID_1852_I2SSR_START_BIT)

#define AW_PID_1852_I2SSR_32_KHZ		(6)
#define AW_PID_1852_I2SSR_32_KHZ_VALUE	\
	(AW_PID_1852_I2SSR_32_KHZ << AW_PID_1852_I2SSR_START_BIT)

#define AW_PID_1852_I2SSR_44P1_KHZ		(7)
#define AW_PID_1852_I2SSR_44P1_KHZ_VALUE	\
	(AW_PID_1852_I2SSR_44P1_KHZ << AW_PID_1852_I2SSR_START_BIT)

#define AW_PID_1852_I2SSR_48_KHZ		(8)
#define AW_PID_1852_I2SSR_48_KHZ_VALUE	\
	(AW_PID_1852_I2SSR_48_KHZ << AW_PID_1852_I2SSR_START_BIT)

#define AW_PID_1852_I2SSR_96_KHZ		(9)
#define AW_PID_1852_I2SSR_96_KHZ_VALUE	\
	(AW_PID_1852_I2SSR_96_KHZ << AW_PID_1852_I2SSR_START_BIT)

#define AW_PID_1852_I2SSR_192KHZ		(10)
#define AW_PID_1852_I2SSR_192KHZ_VALUE	\
	(AW_PID_1852_I2SSR_192KHZ << AW_PID_1852_I2SSR_START_BIT)

#define AW_PID_1852_I2SSR_DEFAULT_VALUE	(8)
#define AW_PID_1852_I2SSR_DEFAULT		\
	(AW_PID_1852_I2SSR_DEFAULT_VALUE << AW_PID_1852_I2SSR_START_BIT)

/* default value of I2SCTRL (0x06) */
/* #define AW_PID_1852_I2SCTRL_DEFAULT		(0x14E8) */

/* I2SCFG1 (0x07) detail */
/* I2S_TX_SLOTVLD bit 13:12 (I2SCFG1 0x07) */
#define AW_PID_1852_I2S_TX_SLOTVLD_START_BIT	(12)
#define AW_PID_1852_I2S_TX_SLOTVLD_BITS_LEN	(2)
#define AW_PID_1852_I2S_TX_SLOTVLD_MASK	\
	(~(((1<<AW_PID_1852_I2S_TX_SLOTVLD_BITS_LEN)-1) << AW_PID_1852_I2S_TX_SLOTVLD_START_BIT))

#define AW_PID_1852_I2S_TX_SLOTVLD_SLOT_0	(0)
#define AW_PID_1852_I2S_TX_SLOTVLD_SLOT_0_VALUE	\
	(AW_PID_1852_I2S_TX_SLOTVLD_SLOT_0 << AW_PID_1852_I2S_TX_SLOTVLD_START_BIT)

#define AW_PID_1852_I2S_TX_SLOTVLD_SLOT_1	(1)
#define AW_PID_1852_I2S_TX_SLOTVLD_SLOT_1_VALUE	\
	(AW_PID_1852_I2S_TX_SLOTVLD_SLOT_1 << AW_PID_1852_I2S_TX_SLOTVLD_START_BIT)

#define AW_PID_1852_I2S_TX_SLOTVLD_SLOT_2	(2)
#define AW_PID_1852_I2S_TX_SLOTVLD_SLOT_2_VALUE	\
	(AW_PID_1852_I2S_TX_SLOTVLD_SLOT_2 << AW_PID_1852_I2S_TX_SLOTVLD_START_BIT)

#define AW_PID_1852_I2S_TX_SLOTVLD_SLOT_3	(3)
#define AW_PID_1852_I2S_TX_SLOTVLD_SLOT_3_VALUE	\
	(AW_PID_1852_I2S_TX_SLOTVLD_SLOT_3 << AW_PID_1852_I2S_TX_SLOTVLD_START_BIT)

#define AW_PID_1852_I2S_TX_SLOTVLD_DEFAULT_VALUE	(0)
#define AW_PID_1852_I2S_TX_SLOTVLD_DEFAULT	\
	(AW_PID_1852_I2S_TX_SLOTVLD_DEFAULT_VALUE << AW_PID_1852_I2S_TX_SLOTVLD_START_BIT)

/* I2S_RX_SLOTVLD bit 11:8 (I2SCFG1 0x07) */
#define AW_PID_1852_I2S_RX_SLOTVLD_START_BIT	(8)
#define AW_PID_1852_I2S_RX_SLOTVLD_BITS_LEN	(4)
#define AW_PID_1852_I2S_RX_SLOTVLD_MASK	\
	(~(((1<<AW_PID_1852_I2S_RX_SLOTVLD_BITS_LEN)-1) << AW_PID_1852_I2S_RX_SLOTVLD_START_BIT))

#define AW_PID_1852_I2S_RX_SLOTVLD_SLOTS_0_AND_1	(3)
#define AW_PID_1852_I2S_RX_SLOTVLD_SLOTS_0_AND_1_VALUE	\
	(AW_PID_1852_I2S_RX_SLOTVLD_SLOTS_0_AND_1 << AW_PID_1852_I2S_RX_SLOTVLD_START_BIT)

#define AW_PID_1852_I2S_RX_SLOTVLD_SLOTS_0_AND_2	(5)
#define AW_PID_1852_I2S_RX_SLOTVLD_SLOTS_0_AND_2_VALUE	\
	(AW_PID_1852_I2S_RX_SLOTVLD_SLOTS_0_AND_2 << AW_PID_1852_I2S_RX_SLOTVLD_START_BIT)

#define AW_PID_1852_I2S_RX_SLOTVLD_SLOTS_0_AND_3	(9)
#define AW_PID_1852_I2S_RX_SLOTVLD_SLOTS_0_AND_3_VALUE	\
	(AW_PID_1852_I2S_RX_SLOTVLD_SLOTS_0_AND_3 << AW_PID_1852_I2S_RX_SLOTVLD_START_BIT)

#define AW_PID_1852_I2S_RX_SLOTVLD_SLOTS_1_AND_2	(6)
#define AW_PID_1852_I2S_RX_SLOTVLD_SLOTS_1_AND_2_VALUE	\
	(AW_PID_1852_I2S_RX_SLOTVLD_SLOTS_1_AND_2 << AW_PID_1852_I2S_RX_SLOTVLD_START_BIT)

#define AW_PID_1852_I2S_RX_SLOTVLD_SLOTS_1_AND_3	(10)
#define AW_PID_1852_I2S_RX_SLOTVLD_SLOTS_1_AND_3_VALUE	\
	(AW_PID_1852_I2S_RX_SLOTVLD_SLOTS_1_AND_3 << AW_PID_1852_I2S_RX_SLOTVLD_START_BIT)

#define AW_PID_1852_I2S_RX_SLOTVLD_SLOTS_2_AND_3	(12)
#define AW_PID_1852_I2S_RX_SLOTVLD_SLOTS_2_AND_3_VALUE	\
	(AW_PID_1852_I2S_RX_SLOTVLD_SLOTS_2_AND_3 << AW_PID_1852_I2S_RX_SLOTVLD_START_BIT)

#define AW_PID_1852_I2S_RX_SLOTVLD_DEFAULT_VALUE	(3)
#define AW_PID_1852_I2S_RX_SLOTVLD_DEFAULT	\
	(AW_PID_1852_I2S_RX_SLOTVLD_DEFAULT_VALUE << AW_PID_1852_I2S_RX_SLOTVLD_START_BIT)

/* CFSEL bit 7:6 (I2SCFG1 0x07) */
#define AW_PID_1852_CFSEL_START_BIT		(6)
#define AW_PID_1852_CFSEL_BITS_LEN		(2)
#define AW_PID_1852_CFSEL_MASK			\
	(~(((1<<AW_PID_1852_CFSEL_BITS_LEN)-1) << AW_PID_1852_CFSEL_START_BIT))

#define AW_PID_1852_CFSEL_HAGC_DATA		(0)
#define AW_PID_1852_CFSEL_HAGC_DATA_VALUE	\
	(AW_PID_1852_CFSEL_HAGC_DATA << AW_PID_1852_CFSEL_START_BIT)

#define AW_PID_1852_CFSEL_IV_SENSE_DATA	(1)
#define AW_PID_1852_CFSEL_IV_SENSE_DATA_VALUE	\
	(AW_PID_1852_CFSEL_IV_SENSE_DATA << AW_PID_1852_CFSEL_START_BIT)

#define AW_PID_1852_CFSEL_IVT_DATA_MAPPING_ACCORDING_TO_I2S_AUDIO_RES	(2)
#define AW_PID_1852_CFSEL_IVT_DATA_MAPPING_ACCORDING_TO_I2S_AUDIO_RES_VALUE	\
	(AW_PID_1852_CFSEL_IVT_DATA_MAPPING_ACCORDING_TO_I2S_AUDIO_RES << AW_PID_1852_CFSEL_START_BIT)

#define AW_PID_1852_CFSEL_IVT_DATA_MAPPING_AS__I_PVDD_VBAT_V_T_SYNC	(3)
#define AW_PID_1852_CFSEL_IVT_DATA_MAPPING_AS__I_PVDD_VBAT_V_T_SYNC_VALUE	\
	(AW_PID_1852_CFSEL_IVT_DATA_MAPPING_AS__I_PVDD_VBAT_V_T_SYNC << AW_PID_1852_CFSEL_START_BIT)

#define AW_PID_1852_CFSEL_DEFAULT_VALUE	(0)
#define AW_PID_1852_CFSEL_DEFAULT		\
	(AW_PID_1852_CFSEL_DEFAULT_VALUE << AW_PID_1852_CFSEL_START_BIT)

/* DRVSTREN bit 5 (I2SCFG1 0x07) */
#define AW_PID_1852_DRVSTREN_START_BIT	(5)
#define AW_PID_1852_DRVSTREN_BITS_LEN	(1)
#define AW_PID_1852_DRVSTREN_MASK		\
	(~(((1<<AW_PID_1852_DRVSTREN_BITS_LEN)-1) << AW_PID_1852_DRVSTREN_START_BIT))

#define AW_PID_1852_DRVSTREN_2MA		(0)
#define AW_PID_1852_DRVSTREN_2MA_VALUE	\
	(AW_PID_1852_DRVSTREN_2MA << AW_PID_1852_DRVSTREN_START_BIT)

#define AW_PID_1852_DRVSTREN_8MA		(1)
#define AW_PID_1852_DRVSTREN_8MA_VALUE	\
	(AW_PID_1852_DRVSTREN_8MA << AW_PID_1852_DRVSTREN_START_BIT)

#define AW_PID_1852_DRVSTREN_DEFAULT_VALUE	(1)
#define AW_PID_1852_DRVSTREN_DEFAULT	\
	(AW_PID_1852_DRVSTREN_DEFAULT_VALUE << AW_PID_1852_DRVSTREN_START_BIT)

/* DOHZ bit 4 (I2SCFG1 0x07) */
#define AW_PID_1852_DOHZ_START_BIT		(4)
#define AW_PID_1852_DOHZ_BITS_LEN		(1)
#define AW_PID_1852_DOHZ_MASK			\
	(~(((1<<AW_PID_1852_DOHZ_BITS_LEN)-1) << AW_PID_1852_DOHZ_START_BIT))

#define AW_PID_1852_DOHZ_ALL_CHANNELS_AVAILABLE	(0)
#define AW_PID_1852_DOHZ_ALL_CHANNELS_AVAILABLE_VALUE	\
	(AW_PID_1852_DOHZ_ALL_CHANNELS_AVAILABLE << AW_PID_1852_DOHZ_START_BIT)

#define AW_PID_1852_DOHZ_HIZ			(1)
#define AW_PID_1852_DOHZ_HIZ_VALUE		\
	(AW_PID_1852_DOHZ_HIZ << AW_PID_1852_DOHZ_START_BIT)

#define AW_PID_1852_DOHZ_DEFAULT_VALUE	(1)
#define AW_PID_1852_DOHZ_DEFAULT		\
	(AW_PID_1852_DOHZ_DEFAULT_VALUE << AW_PID_1852_DOHZ_START_BIT)

/* FSYNC_TYPE bit 3 (I2SCFG1 0x07) */
#define AW_PID_1852_FSYNC_TYPE_START_BIT	(3)
#define AW_PID_1852_FSYNC_TYPE_BITS_LEN	(1)
#define AW_PID_1852_FSYNC_TYPE_MASK		\
	(~(((1<<AW_PID_1852_FSYNC_TYPE_BITS_LEN)-1) << AW_PID_1852_FSYNC_TYPE_START_BIT))

#define AW_PID_1852_FSYNC_TYPE_ONE_SLOT_WIDTH	(0)
#define AW_PID_1852_FSYNC_TYPE_ONE_SLOT_WIDTH_VALUE	\
	(AW_PID_1852_FSYNC_TYPE_ONE_SLOT_WIDTH << AW_PID_1852_FSYNC_TYPE_START_BIT)

#define AW_PID_1852_FSYNC_TYPE_ONE_BCK_CLOCK_CYCLE	(1)
#define AW_PID_1852_FSYNC_TYPE_ONE_BCK_CLOCK_CYCLE_VALUE	\
	(AW_PID_1852_FSYNC_TYPE_ONE_BCK_CLOCK_CYCLE << AW_PID_1852_FSYNC_TYPE_START_BIT)

#define AW_PID_1852_FSYNC_TYPE_DEFAULT_VALUE	(0)
#define AW_PID_1852_FSYNC_TYPE_DEFAULT	\
	(AW_PID_1852_FSYNC_TYPE_DEFAULT_VALUE << AW_PID_1852_FSYNC_TYPE_START_BIT)

/* SLOT_NUM bit 2 (I2SCFG1 0x07) */
#define AW_PID_1852_SLOT_NUM_START_BIT	(2)
#define AW_PID_1852_SLOT_NUM_BITS_LEN	(1)
#define AW_PID_1852_SLOT_NUM_MASK		\
	(~(((1<<AW_PID_1852_SLOT_NUM_BITS_LEN)-1) << AW_PID_1852_SLOT_NUM_START_BIT))

#define AW_PID_1852_SLOT_NUM_2_SLOTS	(0)
#define AW_PID_1852_SLOT_NUM_2_SLOTS_VALUE	\
	(AW_PID_1852_SLOT_NUM_2_SLOTS << AW_PID_1852_SLOT_NUM_START_BIT)

#define AW_PID_1852_SLOT_NUM_4_SLOTS	(1)
#define AW_PID_1852_SLOT_NUM_4_SLOTS_VALUE	\
	(AW_PID_1852_SLOT_NUM_4_SLOTS << AW_PID_1852_SLOT_NUM_START_BIT)

#define AW_PID_1852_SLOT_NUM_DEFAULT_VALUE	(0)
#define AW_PID_1852_SLOT_NUM_DEFAULT	\
	(AW_PID_1852_SLOT_NUM_DEFAULT_VALUE << AW_PID_1852_SLOT_NUM_START_BIT)

/* I2SCHS bit 1 (I2SCFG1 0x07) */
#define AW_PID_1852_I2SCHS_START_BIT	(1)
#define AW_PID_1852_I2SCHS_BITS_LEN		(1)
#define AW_PID_1852_I2SCHS_MASK			\
	(~(((1<<AW_PID_1852_I2SCHS_BITS_LEN)-1) << AW_PID_1852_I2SCHS_START_BIT))

#define AW_PID_1852_I2SCHS_LEFT_CHANNEL	(0)
#define AW_PID_1852_I2SCHS_LEFT_CHANNEL_VALUE	\
	(AW_PID_1852_I2SCHS_LEFT_CHANNEL << AW_PID_1852_I2SCHS_START_BIT)

#define AW_PID_1852_I2SCHS_RIGHT_CHANNEL	(1)
#define AW_PID_1852_I2SCHS_RIGHT_CHANNEL_VALUE	\
	(AW_PID_1852_I2SCHS_RIGHT_CHANNEL << AW_PID_1852_I2SCHS_START_BIT)

#define AW_PID_1852_I2SCHS_DEFAULT_VALUE	(0)
#define AW_PID_1852_I2SCHS_DEFAULT		\
	(AW_PID_1852_I2SCHS_DEFAULT_VALUE << AW_PID_1852_I2SCHS_START_BIT)

/* I2STXEN bit 0 (I2SCFG1 0x07) */
#define AW_PID_1852_I2STXEN_START_BIT	(0)
#define AW_PID_1852_I2STXEN_BITS_LEN	(1)
#define AW_PID_1852_I2STXEN_MASK		\
	(~(((1<<AW_PID_1852_I2STXEN_BITS_LEN)-1) << AW_PID_1852_I2STXEN_START_BIT))

#define AW_PID_1852_I2STXEN_DISABLE		(0)
#define AW_PID_1852_I2STXEN_DISABLE_VALUE	\
	(AW_PID_1852_I2STXEN_DISABLE << AW_PID_1852_I2STXEN_START_BIT)

#define AW_PID_1852_I2STXEN_ENABLE		(1)
#define AW_PID_1852_I2STXEN_ENABLE_VALUE	\
	(AW_PID_1852_I2STXEN_ENABLE << AW_PID_1852_I2STXEN_START_BIT)

#define AW_PID_1852_I2STXEN_DEFAULT_VALUE	(0)
#define AW_PID_1852_I2STXEN_DEFAULT		\
	(AW_PID_1852_I2STXEN_DEFAULT_VALUE << AW_PID_1852_I2STXEN_START_BIT)

/* default value of I2SCFG1 (0x07) */
/* #define AW_PID_1852_I2SCFG1_DEFAULT		(0x0330) */

/* HAGCCFG1 (0x09) detail */
/* RVTH bit 15:8 (HAGCCFG1 0x09) */
#define AW_PID_1852_RVTH_START_BIT		(8)
#define AW_PID_1852_RVTH_BITS_LEN		(8)
#define AW_PID_1852_RVTH_MASK			\
	(~(((1<<AW_PID_1852_RVTH_BITS_LEN)-1) << AW_PID_1852_RVTH_START_BIT))

#define AW_PID_1852_RVTH_DEFAULT_VALUE	(0x39)
#define AW_PID_1852_RVTH_DEFAULT		\
	(AW_PID_1852_RVTH_DEFAULT_VALUE << AW_PID_1852_RVTH_START_BIT)

/* AVTH bit 7:0 (HAGCCFG1 0x09) */
#define AW_PID_1852_AVTH_START_BIT		(0)
#define AW_PID_1852_AVTH_BITS_LEN		(8)
#define AW_PID_1852_AVTH_MASK			\
	(~(((1<<AW_PID_1852_AVTH_BITS_LEN)-1) << AW_PID_1852_AVTH_START_BIT))

#define AW_PID_1852_AVTH_DEFAULT_VALUE	(0x40)
#define AW_PID_1852_AVTH_DEFAULT		\
	(AW_PID_1852_AVTH_DEFAULT_VALUE << AW_PID_1852_AVTH_START_BIT)

/* default value of HAGCCFG1 (0x09) */
/* #define AW_PID_1852_HAGCCFG1_DEFAULT		(0x3940) */

/* HAGCCFG2 (0x0A) detail */
/* ATTH bit 15:0 (HAGCCFG2 0x0A) */
#define AW_PID_1852_ATTH_START_BIT		(0)
#define AW_PID_1852_ATTH_BITS_LEN		(16)
#define AW_PID_1852_ATTH_MASK			\
	(~(((1<<AW_PID_1852_ATTH_BITS_LEN)-1) << AW_PID_1852_ATTH_START_BIT))

#define AW_PID_1852_ATTH_RESERVED		(0)
#define AW_PID_1852_ATTH_RESERVED_VALUE	\
	(AW_PID_1852_ATTH_RESERVED << AW_PID_1852_ATTH_START_BIT)

#define AW_PID_1852_ATTH_DEFAULT_VALUE	(0x0030)
#define AW_PID_1852_ATTH_DEFAULT		\
	(AW_PID_1852_ATTH_DEFAULT_VALUE << AW_PID_1852_ATTH_START_BIT)

/* default value of HAGCCFG2 (0x0A) */
/* #define AW_PID_1852_HAGCCFG2_DEFAULT		(0x0030) */

/* HAGCCFG3 (0x0B) detail */
/* RTTH bit 15:0 (HAGCCFG3 0x0B) */
#define AW_PID_1852_RTTH_START_BIT		(0)
#define AW_PID_1852_RTTH_BITS_LEN		(16)
#define AW_PID_1852_RTTH_MASK			\
	(~(((1<<AW_PID_1852_RTTH_BITS_LEN)-1) << AW_PID_1852_RTTH_START_BIT))

#define AW_PID_1852_RTTH_RESERVED		(0)
#define AW_PID_1852_RTTH_RESERVED_VALUE	\
	(AW_PID_1852_RTTH_RESERVED << AW_PID_1852_RTTH_START_BIT)

#define AW_PID_1852_RTTH_DEFAULT_VALUE	(0x01E0)
#define AW_PID_1852_RTTH_DEFAULT		\
	(AW_PID_1852_RTTH_DEFAULT_VALUE << AW_PID_1852_RTTH_START_BIT)

/* I2S CCO_UMX */
#define AW_PID_1852_I2S_CCO_MUX_START_BIT		(14)
#define AW_PID_1852_I2S_CCO_MUX_BITS_LEN		(1)
#define AW_PID_1852_I2S_CCO_MUX_MASK			\
	(~(((1<<AW_PID_1852_I2S_CCO_MUX_BITS_LEN)-1)<<AW_PID_1852_I2S_CCO_MUX_START_BIT))

#define AW_PID_1852_I2S_CCO_MUX_8_16_32KHZ_BIT_VALUE		(0)
#define AW_PID_1852_I2S_CCO_MUX_8_16_32KHZ_VALUE			\
	(AW_PID_1852_I2S_CCO_MUX_8_16_32KHZ_BIT_VALUE<<AW_PID_1852_I2S_CCO_MUX_START_BIT)


#define AW_PID_1852_I2S_CCO_MUX_EXC_8_16_32KHZ_BIT_VALUE	(1)
#define AW_PID_1852_I2S_CCO_MUX_EXC_8_16_32KHZ_VALUE			\
	(AW_PID_1852_I2S_CCO_MUX_EXC_8_16_32KHZ_BIT_VALUE<<AW_PID_1852_I2S_CCO_MUX_START_BIT)

/* default value of HAGCCFG3 (0x0B) */
/* #define AW_PID_1852_HAGCCFG3_DEFAULT		(0x01E0) */

/* HAGCCFG4 (0x0C) detail */
/* VOL bit 15:8 (HAGCCFG4 0x0C) */
#define AW_PID_1852_MUTE_VOL  (90 * 2)
#define AW_PID_1852_VOL_STEP_DB   (6 * 2)

#define AW_PID_1852_VOL_START_BIT		(8)
#define AW_PID_1852_VOL_BITS_LEN		(8)
#define AW_PID_1852_VOL_MASK			\
	(~(((1<<AW_PID_1852_VOL_BITS_LEN)-1) << AW_PID_1852_VOL_START_BIT))

#define AW_PID_1852_VOL_DEFAULT_VALUE	(0)
#define AW_PID_1852_VOL_DEFAULT			\
	(AW_PID_1852_VOL_DEFAULT_VALUE << AW_PID_1852_VOL_START_BIT)

/* HOLDTH bit 7:0 (HAGCCFG4 0x0C) */
#define AW_PID_1852_HOLDTH_START_BIT	(0)
#define AW_PID_1852_HOLDTH_BITS_LEN		(8)
#define AW_PID_1852_HOLDTH_MASK			\
	(~(((1<<AW_PID_1852_HOLDTH_BITS_LEN)-1) << AW_PID_1852_HOLDTH_START_BIT))

#define AW_PID_1852_HOLDTH_RESERVED		(0)
#define AW_PID_1852_HOLDTH_RESERVED_VALUE	\
	(AW_PID_1852_HOLDTH_RESERVED << AW_PID_1852_HOLDTH_START_BIT)

#define AW_PID_1852_HOLDTH_DEFAULT_VALUE	(0x64)
#define AW_PID_1852_HOLDTH_DEFAULT		\
	(AW_PID_1852_HOLDTH_DEFAULT_VALUE << AW_PID_1852_HOLDTH_START_BIT)

/* default value of HAGCCFG4 (0x0C) */
/* #define AW_PID_1852_HAGCCFG4_DEFAULT		(0x0064) */

/* HAGCST (0x10) detail */
/* SPK_GAIN_ST bit 10:8 (HAGCST 0x10) */
#define AW_PID_1852_SPK_GAIN_ST_START_BIT	(8)
#define AW_PID_1852_SPK_GAIN_ST_BITS_LEN	(3)
#define AW_PID_1852_SPK_GAIN_ST_MASK	\
	(~(((1<<AW_PID_1852_SPK_GAIN_ST_BITS_LEN)-1) << AW_PID_1852_SPK_GAIN_ST_START_BIT))

#define AW_PID_1852_SPK_GAIN_ST_AV7		(0)
#define AW_PID_1852_SPK_GAIN_ST_AV7_VALUE	\
	(AW_PID_1852_SPK_GAIN_ST_AV7 << AW_PID_1852_SPK_GAIN_ST_START_BIT)

#define AW_PID_1852_SPK_GAIN_ST_AV8		(1)
#define AW_PID_1852_SPK_GAIN_ST_AV8_VALUE	\
	(AW_PID_1852_SPK_GAIN_ST_AV8 << AW_PID_1852_SPK_GAIN_ST_START_BIT)

#define AW_PID_1852_SPK_GAIN_ST_AV10	(2)
#define AW_PID_1852_SPK_GAIN_ST_AV10_VALUE	\
	(AW_PID_1852_SPK_GAIN_ST_AV10 << AW_PID_1852_SPK_GAIN_ST_START_BIT)

#define AW_PID_1852_SPK_GAIN_ST_AV14	(3)
#define AW_PID_1852_SPK_GAIN_ST_AV14_VALUE	\
	(AW_PID_1852_SPK_GAIN_ST_AV14 << AW_PID_1852_SPK_GAIN_ST_START_BIT)

#define AW_PID_1852_SPK_GAIN_ST_AV16	(4)
#define AW_PID_1852_SPK_GAIN_ST_AV16_VALUE	\
	(AW_PID_1852_SPK_GAIN_ST_AV16 << AW_PID_1852_SPK_GAIN_ST_START_BIT)

#define AW_PID_1852_SPK_GAIN_ST_AV20	(5)
#define AW_PID_1852_SPK_GAIN_ST_AV20_VALUE	\
	(AW_PID_1852_SPK_GAIN_ST_AV20 << AW_PID_1852_SPK_GAIN_ST_START_BIT)

#define AW_PID_1852_SPK_GAIN_ST_DEFAULT_VALUE	(0)
#define AW_PID_1852_SPK_GAIN_ST_DEFAULT	\
	(AW_PID_1852_SPK_GAIN_ST_DEFAULT_VALUE << AW_PID_1852_SPK_GAIN_ST_START_BIT)

/* BSTVOUT_ST bit 5:0 (HAGCST 0x10) */
#define AW_PID_1852_BSTVOUT_ST_START_BIT	(0)
#define AW_PID_1852_BSTVOUT_ST_BITS_LEN	(6)
#define AW_PID_1852_BSTVOUT_ST_MASK		\
	(~(((1<<AW_PID_1852_BSTVOUT_ST_BITS_LEN)-1) << AW_PID_1852_BSTVOUT_ST_START_BIT))

#define AW_PID_1852_BSTVOUT_ST_3P125V	(0)
#define AW_PID_1852_BSTVOUT_ST_3P125V_VALUE	\
	(AW_PID_1852_BSTVOUT_ST_3P125V << AW_PID_1852_BSTVOUT_ST_START_BIT)

#define AW_PID_1852_BSTVOUT_ST_3P25V	(1)
#define AW_PID_1852_BSTVOUT_ST_3P25V_VALUE	\
	(AW_PID_1852_BSTVOUT_ST_3P25V << AW_PID_1852_BSTVOUT_ST_START_BIT)

#define AW_PID_1852_BSTVOUT_ST_3P375V	(2)
#define AW_PID_1852_BSTVOUT_ST_3P375V_VALUE	\
	(AW_PID_1852_BSTVOUT_ST_3P375V << AW_PID_1852_BSTVOUT_ST_START_BIT)

#define AW_PID_1852_BSTVOUT_ST_3P5V		(3)
#define AW_PID_1852_BSTVOUT_ST_3P5V_VALUE	\
	(AW_PID_1852_BSTVOUT_ST_3P5V << AW_PID_1852_BSTVOUT_ST_START_BIT)

#define AW_PID_1852_BSTVOUT_ST_3P625V	(4)
#define AW_PID_1852_BSTVOUT_ST_3P625V_VALUE	\
	(AW_PID_1852_BSTVOUT_ST_3P625V << AW_PID_1852_BSTVOUT_ST_START_BIT)

#define AW_PID_1852_BSTVOUT_ST_3P75V	(5)
#define AW_PID_1852_BSTVOUT_ST_3P75V_VALUE	\
	(AW_PID_1852_BSTVOUT_ST_3P75V << AW_PID_1852_BSTVOUT_ST_START_BIT)

#define AW_PID_1852_BSTVOUT_ST_11V		(63)
#define AW_PID_1852_BSTVOUT_ST_11V_VALUE	\
	(AW_PID_1852_BSTVOUT_ST_11V << AW_PID_1852_BSTVOUT_ST_START_BIT)

#define AW_PID_1852_BSTVOUT_ST_DEFAULT_VALUE	(0)
#define AW_PID_1852_BSTVOUT_ST_DEFAULT	\
	(AW_PID_1852_BSTVOUT_ST_DEFAULT_VALUE << AW_PID_1852_BSTVOUT_ST_START_BIT)

/* default value of HAGCST (0x10) */
/* #define AW_PID_1852_HAGCST_DEFAULT		(0x0000) */

/* VBAT (0x12) detail */
/* VBAT_DET bit 9:0 (VBAT 0x12) */
#define AW_PID_1852_VBAT_DET_START_BIT	(0)
#define AW_PID_1852_VBAT_DET_BITS_LEN	(10)
#define AW_PID_1852_VBAT_DET_MASK		\
	(~(((1<<AW_PID_1852_VBAT_DET_BITS_LEN)-1) << AW_PID_1852_VBAT_DET_START_BIT))

#define AW_PID_1852_VBAT_DET_DEFAULT_VALUE	(0x263)
#define AW_PID_1852_VBAT_DET_DEFAULT	\
	(AW_PID_1852_VBAT_DET_DEFAULT_VALUE << AW_PID_1852_VBAT_DET_START_BIT)

/* default value of VBAT (0x12) */
/* #define AW_PID_1852_VBAT_DEFAULT		(0x0263) */

/* TEMP (0x13) detail */
/* TEMP_DET bit 9:0 (TEMP 0x13) */
#define AW_PID_1852_TEMP_DET_START_BIT	(0)
#define AW_PID_1852_TEMP_DET_BITS_LEN	(10)
#define AW_PID_1852_TEMP_DET_MASK		\
	(~(((1<<AW_PID_1852_TEMP_DET_BITS_LEN)-1) << AW_PID_1852_TEMP_DET_START_BIT))

#define AW_PID_1852_TEMP_DET_MINUS_40DEGREE	(0x3D8)
#define AW_PID_1852_TEMP_DET_MINUS_40DEGREE_VALUE	\
	(AW_PID_1852_TEMP_DET_MINUS_40DEGREE << AW_PID_1852_TEMP_DET_START_BIT)

#define AW_PID_1852_TEMP_DET_0_DEGREE	(0x00)
#define AW_PID_1852_TEMP_DET_0_DEGREE_VALUE	\
	(AW_PID_1852_TEMP_DET_0_DEGREE << AW_PID_1852_TEMP_DET_START_BIT)

#define AW_PID_1852_TEMP_DET_1_DEGREE	(0x01)
#define AW_PID_1852_TEMP_DET_1_DEGREE_VALUE	\
	(AW_PID_1852_TEMP_DET_1_DEGREE << AW_PID_1852_TEMP_DET_START_BIT)

#define AW_PID_1852_TEMP_DET_25_DEGREE	(0x19)
#define AW_PID_1852_TEMP_DET_25_DEGREE_VALUE	\
	(AW_PID_1852_TEMP_DET_25_DEGREE << AW_PID_1852_TEMP_DET_START_BIT)

#define AW_PID_1852_TEMP_DET_55_DEGREE	(0x37)
#define AW_PID_1852_TEMP_DET_55_DEGREE_VALUE	\
	(AW_PID_1852_TEMP_DET_55_DEGREE << AW_PID_1852_TEMP_DET_START_BIT)

#define AW_PID_1852_TEMP_DET_DEFAULT_VALUE	(0x019)
#define AW_PID_1852_TEMP_DET_DEFAULT	\
	(AW_PID_1852_TEMP_DET_DEFAULT_VALUE << AW_PID_1852_TEMP_DET_START_BIT)

/* default value of TEMP (0x13) */
/* #define AW_PID_1852_TEMP_DEFAULT		(0x0019) */

/* PVDD (0x14) detail */
/* PVDD_DET bit 9:0 (PVDD 0x14) */
#define AW_PID_1852_PVDD_DET_START_BIT	(0)
#define AW_PID_1852_PVDD_DET_BITS_LEN	(10)
#define AW_PID_1852_PVDD_DET_MASK		\
	(~(((1<<AW_PID_1852_PVDD_DET_BITS_LEN)-1) << AW_PID_1852_PVDD_DET_START_BIT))

#define AW_PID_1852_PVDD_DET_DEFAULT_VALUE	(0x263)
#define AW_PID_1852_PVDD_DET_DEFAULT	\
	(AW_PID_1852_PVDD_DET_DEFAULT_VALUE << AW_PID_1852_PVDD_DET_START_BIT)

/* default value of PVDD (0x14) */
/* #define AW_PID_1852_PVDD_DEFAULT		(0x0263) */

/* BSTCTRL1 (0x60) detail */
/* BST_RTH bit 13:8 (BSTCTRL1 0x60) */
#define AW_PID_1852_BST_RTH_START_BIT	(8)
#define AW_PID_1852_BST_RTH_BITS_LEN	(6)
#define AW_PID_1852_BST_RTH_MASK		\
	(~(((1<<AW_PID_1852_BST_RTH_BITS_LEN)-1) << AW_PID_1852_BST_RTH_START_BIT))

#define AW_PID_1852_BST_RTH_DEFAULT_VALUE	(4)
#define AW_PID_1852_BST_RTH_DEFAULT		\
	(AW_PID_1852_BST_RTH_DEFAULT_VALUE << AW_PID_1852_BST_RTH_START_BIT)

/* BST_ATH bit 5:0 (BSTCTRL1 0x60) */
#define AW_PID_1852_BST_ATH_START_BIT	(0)
#define AW_PID_1852_BST_ATH_BITS_LEN	(6)
#define AW_PID_1852_BST_ATH_MASK		\
	(~(((1<<AW_PID_1852_BST_ATH_BITS_LEN)-1) << AW_PID_1852_BST_ATH_START_BIT))

#define AW_PID_1852_BST_ATH_DEFAULT_VALUE	(2)
#define AW_PID_1852_BST_ATH_DEFAULT		\
	(AW_PID_1852_BST_ATH_DEFAULT_VALUE << AW_PID_1852_BST_ATH_START_BIT)

/* default value of BSTCTRL1 (0x60) */
/* #define AW_PID_1852_BSTCTRL1_DEFAULT		(0x0402) */

/* BSTCTRL2 (0x61) detail */
/* VOUT_CTMD bit 15 (BSTCTRL2 0x61) */
#define AW_PID_1852_VOUT_CTMD_START_BIT	(15)
#define AW_PID_1852_VOUT_CTMD_BITS_LEN	(1)
#define AW_PID_1852_VOUT_CTMD_MASK		\
	(~(((1<<AW_PID_1852_VOUT_CTMD_BITS_LEN)-1) << AW_PID_1852_VOUT_CTMD_START_BIT))

#define AW_PID_1852_VOUT_CTMD_PVDD_CONTROLLED_BY_VREF_125MVSTEP	(0)
#define AW_PID_1852_VOUT_CTMD_PVDD_CONTROLLED_BY_VREF_125MVSTEP_VALUE	\
	(AW_PID_1852_VOUT_CTMD_PVDD_CONTROLLED_BY_VREF_125MVSTEP << AW_PID_1852_VOUT_CTMD_START_BIT)

#define AW_PID_1852_VOUT_CTMD_PVDD_CONTROLLED_BY_VFB_4_LEVELS	(1)
#define AW_PID_1852_VOUT_CTMD_PVDD_CONTROLLED_BY_VFB_4_LEVELS_VALUE	\
	(AW_PID_1852_VOUT_CTMD_PVDD_CONTROLLED_BY_VFB_4_LEVELS << AW_PID_1852_VOUT_CTMD_START_BIT)

#define AW_PID_1852_VOUT_CTMD_DEFAULT_VALUE	(0)
#define AW_PID_1852_VOUT_CTMD_DEFAULT	\
	(AW_PID_1852_VOUT_CTMD_DEFAULT_VALUE << AW_PID_1852_VOUT_CTMD_START_BIT)

/* BST_MODE bit 14:12 (BSTCTRL2 0x61) */
#define AW_PID_1852_BST_MODE_START_BIT	(12)
#define AW_PID_1852_BST_MODE_BITS_LEN	(3)
#define AW_PID_1852_BST_MODE_MASK		\
	(~(((1<<AW_PID_1852_BST_MODE_BITS_LEN)-1) << AW_PID_1852_BST_MODE_START_BIT))

#define AW_PID_1852_BST_MODE_TRANSPARENT_MODE	(0)
#define AW_PID_1852_BST_MODE_TRANSPARENT_MODE_VALUE	\
	(AW_PID_1852_BST_MODE_TRANSPARENT_MODE << AW_PID_1852_BST_MODE_START_BIT)

#define AW_PID_1852_BST_MODE_FORCE_BOOST_MODE	(1)
#define AW_PID_1852_BST_MODE_FORCE_BOOST_MODE_VALUE	\
	(AW_PID_1852_BST_MODE_FORCE_BOOST_MODE << AW_PID_1852_BST_MODE_START_BIT)

#define AW_PID_1852_BST_MODE_TEST_BOOST_MODE	(3)
#define AW_PID_1852_BST_MODE_TEST_BOOST_MODE_VALUE	\
	(AW_PID_1852_BST_MODE_TEST_BOOST_MODE << AW_PID_1852_BST_MODE_START_BIT)

#define AW_PID_1852_BST_MODE_CLASS_G_MODE	(5)
#define AW_PID_1852_BST_MODE_CLASS_G_MODE_VALUE	\
	(AW_PID_1852_BST_MODE_CLASS_G_MODE << AW_PID_1852_BST_MODE_START_BIT)

#define AW_PID_1852_BST_MODE_DEFAULT_VALUE	(0x6)
#define AW_PID_1852_BST_MODE_DEFAULT	\
	(AW_PID_1852_BST_MODE_DEFAULT_VALUE << AW_PID_1852_BST_MODE_START_BIT)

/* BST_TDEG bit 10:8 (BSTCTRL2 0x61) */
#define AW_PID_1852_BST_TDEG_START_BIT	(8)
#define AW_PID_1852_BST_TDEG_BITS_LEN	(3)
#define AW_PID_1852_BST_TDEG_MASK		\
	(~(((1<<AW_PID_1852_BST_TDEG_BITS_LEN)-1) << AW_PID_1852_BST_TDEG_START_BIT))

#define AW_PID_1852_BST_TDEG_0P33_MS	(0)
#define AW_PID_1852_BST_TDEG_0P33_MS_VALUE	\
	(AW_PID_1852_BST_TDEG_0P33_MS << AW_PID_1852_BST_TDEG_START_BIT)

#define AW_PID_1852_BST_TDEG_1P40_MS	(1)
#define AW_PID_1852_BST_TDEG_1P40_MS_VALUE	\
	(AW_PID_1852_BST_TDEG_1P40_MS << AW_PID_1852_BST_TDEG_START_BIT)

#define AW_PID_1852_BST_TDEG_5P60_MS	(2)
#define AW_PID_1852_BST_TDEG_5P60_MS_VALUE	\
	(AW_PID_1852_BST_TDEG_5P60_MS << AW_PID_1852_BST_TDEG_START_BIT)

#define AW_PID_1852_BST_TDEG_21P30_MS	(3)
#define AW_PID_1852_BST_TDEG_21P30_MS_VALUE	\
	(AW_PID_1852_BST_TDEG_21P30_MS << AW_PID_1852_BST_TDEG_START_BIT)

#define AW_PID_1852_BST_TDEG_44_MS		(4)
#define AW_PID_1852_BST_TDEG_44_MS_VALUE	\
	(AW_PID_1852_BST_TDEG_44_MS << AW_PID_1852_BST_TDEG_START_BIT)

#define AW_PID_1852_BST_TDEG_88_MS		(5)
#define AW_PID_1852_BST_TDEG_88_MS_VALUE	\
	(AW_PID_1852_BST_TDEG_88_MS << AW_PID_1852_BST_TDEG_START_BIT)

#define AW_PID_1852_BST_TDEG_352_MS		(6)
#define AW_PID_1852_BST_TDEG_352_MS_VALUE	\
	(AW_PID_1852_BST_TDEG_352_MS << AW_PID_1852_BST_TDEG_START_BIT)

#define AW_PID_1852_BST_TDEG_1P4_S		(7)
#define AW_PID_1852_BST_TDEG_1P4_S_VALUE	\
	(AW_PID_1852_BST_TDEG_1P4_S << AW_PID_1852_BST_TDEG_START_BIT)

#define AW_PID_1852_BST_TDEG_DEFAULT_VALUE	(0x6)
#define AW_PID_1852_BST_TDEG_DEFAULT	\
	(AW_PID_1852_BST_TDEG_DEFAULT_VALUE << AW_PID_1852_BST_TDEG_START_BIT)

/* VOUT_VFBSET bit 7:6 (BSTCTRL2 0x61) */
#define AW_PID_1852_VOUT_VFBSET_START_BIT	(6)
#define AW_PID_1852_VOUT_VFBSET_BITS_LEN	(2)
#define AW_PID_1852_VOUT_VFBSET_MASK	\
	(~(((1<<AW_PID_1852_VOUT_VFBSET_BITS_LEN)-1) << AW_PID_1852_VOUT_VFBSET_START_BIT))

#define AW_PID_1852_VOUT_VFBSET_8P5V	(0)
#define AW_PID_1852_VOUT_VFBSET_8P5V_VALUE	\
	(AW_PID_1852_VOUT_VFBSET_8P5V << AW_PID_1852_VOUT_VFBSET_START_BIT)

#define AW_PID_1852_VOUT_VFBSET_9P5V	(1)
#define AW_PID_1852_VOUT_VFBSET_9P5V_VALUE	\
	(AW_PID_1852_VOUT_VFBSET_9P5V << AW_PID_1852_VOUT_VFBSET_START_BIT)

#define AW_PID_1852_VOUT_VFBSET_10P5V	(2)
#define AW_PID_1852_VOUT_VFBSET_10P5V_VALUE	\
	(AW_PID_1852_VOUT_VFBSET_10P5V << AW_PID_1852_VOUT_VFBSET_START_BIT)

/*
 *#define AW_PID_1852_VOUT_VFBSET_10P5V	(3)
 *#define AW_PID_1852_VOUT_VFBSET_10P5V_VALUE	\
 *	(AW_PID_1852_VOUT_VFBSET_10P5V << AW_PID_1852_VOUT_VFBSET_START_BIT)
 */

#define AW_PID_1852_VOUT_VFBSET_DEFAULT_VALUE	(1)
#define AW_PID_1852_VOUT_VFBSET_DEFAULT	\
	(AW_PID_1852_VOUT_VFBSET_DEFAULT_VALUE << AW_PID_1852_VOUT_VFBSET_START_BIT)

/* VOUT_VREFSET bit 5:0 (BSTCTRL2 0x61) */
#define AW_PID_1852_VOUT_VREFSET_START_BIT	(0)
#define AW_PID_1852_VOUT_VREFSET_BITS_LEN	(6)
#define AW_PID_1852_VOUT_VREFSET_MASK	\
	(~(((1<<AW_PID_1852_VOUT_VREFSET_BITS_LEN)-1) << AW_PID_1852_VOUT_VREFSET_START_BIT))

#define AW_PID_1852_VOUT_VREFSET_3P125V	(0)
#define AW_PID_1852_VOUT_VREFSET_3P125V_VALUE	\
	(AW_PID_1852_VOUT_VREFSET_3P125V << AW_PID_1852_VOUT_VREFSET_START_BIT)

#define AW_PID_1852_VOUT_VREFSET_3P25V	(1)
#define AW_PID_1852_VOUT_VREFSET_3P25V_VALUE	\
	(AW_PID_1852_VOUT_VREFSET_3P25V << AW_PID_1852_VOUT_VREFSET_START_BIT)

#define AW_PID_1852_VOUT_VREFSET_3P375V	(2)
#define AW_PID_1852_VOUT_VREFSET_3P375V_VALUE	\
	(AW_PID_1852_VOUT_VREFSET_3P375V << AW_PID_1852_VOUT_VREFSET_START_BIT)

#define AW_PID_1852_VOUT_VREFSET_3P5V	(3)
#define AW_PID_1852_VOUT_VREFSET_3P5V_VALUE	\
	(AW_PID_1852_VOUT_VREFSET_3P5V << AW_PID_1852_VOUT_VREFSET_START_BIT)

#define AW_PID_1852_VOUT_VREFSET_3P625V	(4)
#define AW_PID_1852_VOUT_VREFSET_3P625V_VALUE	\
	(AW_PID_1852_VOUT_VREFSET_3P625V << AW_PID_1852_VOUT_VREFSET_START_BIT)

#define AW_PID_1852_VOUT_VREFSET_3P75V	(5)
#define AW_PID_1852_VOUT_VREFSET_3P75V_VALUE	\
	(AW_PID_1852_VOUT_VREFSET_3P75V << AW_PID_1852_VOUT_VREFSET_START_BIT)

#define AW_PID_1852_VOUT_VREFSET_11V	(63)
#define AW_PID_1852_VOUT_VREFSET_11V_VALUE	\
	(AW_PID_1852_VOUT_VREFSET_11V << AW_PID_1852_VOUT_VREFSET_START_BIT)

#define AW_PID_1852_VOUT_VREFSET_DEFAULT_VALUE	(0x33)
#define AW_PID_1852_VOUT_VREFSET_DEFAULT	\
	(AW_PID_1852_VOUT_VREFSET_DEFAULT_VALUE << AW_PID_1852_VOUT_VREFSET_START_BIT)

/* default value of BSTCTRL2 (0x61) */
/* #define AW_PID_1852_BSTCTRL2_DEFAULT		(0x6673) */

/* detail information of registers end */
/********************************************
 * Volume Coefficient
 *******************************************/
#define AW_PID_1852_VOL_STEP		(6 * 2)

/********************************************
 * Vcalb
 *******************************************/
#define AW_PID_1852_EF_VSN_GESLP_MASK		(~0x03ff)
#define AW_PID_1852_EF_VSN_GESLP_SIGN_MASK		(~0x0200)
#define AW_PID_1852_EF_VSN_GESLP_NEG		(~0xfc00)

#define AW_PID_1852_EF_ISN_GESLP_MASK		(~0x03ff)
#define AW_PID_1852_EF_ISN_GESLP_SIGN_MASK		(~0x0200)
#define AW_PID_1852_EF_ISN_GESLP_NEG		(~0xfc00)

#define AW_PID_1852_CABL_BASE_VALUE			(1000)
#define AW_PID_1852_ICABLK_FACTOR			(1)
#define AW_PID_1852_VCABLK_FACTOR			(1)

#define AW_PID_1852_VCAL_FACTOR			(1<<13)

#define AW_PID_1852_MONITOR_VBAT_RANGE		(6025)
#define AW_PID_1852_MONITOR_INT_10BIT		(1023)
#define AW_PID_1852_MONITOR_TEMP_SIGN_MASK		(~(1<<9))
#define AW_PID_1852_MONITOR_TEMP_NEG_MASK		(0XFC00)
/********************************************
 * Dither
 *******************************************/
#define AW_PID_1852_DITHER_START_BIT	(7)
#define AW_PID_1852_DITHER_BITS_LEN	(1)
#define AW_PID_1852_DITHER_MASK	\
	(~(((1<<AW_PID_1852_DITHER_BITS_LEN)-1) << AW_PID_1852_DITHER_START_BIT))

#define AW_PID_1852_DITHER_DISABLE	(0)
#define AW_PID_1852_DITHER_DISABLE_VALUE	\
	(AW_PID_1852_DITHER_DISABLE << AW_PID_1852_DITHER_START_BIT)

#define AW_PID_1852_DITHER_ENABLE	(1)
#define AW_PID_1852_DITHER_ENABLE_VALUE	\
	(AW_PID_1852_DITHER_ENABLE << AW_PID_1852_DITHER_START_BIT)

#endif  /* #ifndef  __AW_PID_1852_REG_H__ */
